Commit f0c5dfd6 authored by hongzhi wang's avatar hongzhi wang

UE nr parms init bug fix

parent a75834ca
......@@ -928,3 +928,45 @@ void nr_lte_ue_transport(PHY_VARS_UE *ue,int abstraction_flag) {
ue->dlsch_MCH[0] = new_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,MAX_TURBO_ITERATIONS_MBSFN,ue->frame_parms.N_RB_DL,0);
}*/
void phy_init_nr_top(NR_DL_FRAME_PARMS *frame_parms)
{
crcTableInit();
ccodedot11_init();
ccodedot11_init_inv();
ccodelte_init();
ccodelte_init_inv();
//treillis_table_init();
phy_generate_viterbi_tables();
phy_generate_viterbi_tables_lte();
//init_td8();
//init_td16();
#ifdef __AVX2__
//init_td16avx2();
#endif
init_context_synchro_nr(frame_parms);
generate_ul_reference_signal_sequences(SHRT_MAX);
//lte_sync_time_init(frame_parms);
//generate_ul_ref_sigs();
//generate_ul_ref_sigs_rx();
//generate_64qam_table();
//generate_16qam_table();
//generate_RIV_tables();
//init_unscrambling_lut();
//init_scrambling_lut();
//set_taus_seed(1328);
}
......@@ -34,6 +34,131 @@ int nr_init_frame_parms(nfapi_config_request_t* config,
int Ncp = config->subframe_config.dl_cyclic_prefix_type.value;
int mu = config->subframe_config.numerology_index_mu.value;
#if DISABLE_LOG_X
printf("Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, N_RB, Ncp);
#else
LOG_I(PHY,"Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, N_RB, Ncp);
#endif
if (Ncp == EXTENDED)
AssertFatal(mu == NR_MU_2,"Invalid cyclic prefix %d for numerology index %d\n", Ncp, mu);
switch(mu) {
case NR_MU_0: //15kHz scs
frame_parms->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_0];
frame_parms->slots_per_subframe = nr_slots_per_subframe[NR_MU_0];
break;
case NR_MU_1: //30kHz scs
frame_parms->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_1];
frame_parms->slots_per_subframe = nr_slots_per_subframe[NR_MU_1];
switch(N_RB){
case 11:
case 24:
case 38:
case 78:
case 51:
case 65:
case 106: //40 MHz
if (frame_parms->threequarter_fs) {
frame_parms->ofdm_symbol_size = 1536;
frame_parms->first_carrier_offset = 900; //1536 - 636
frame_parms->nb_prefix_samples0 = 132;
frame_parms->nb_prefix_samples = 108;
}
else {
frame_parms->ofdm_symbol_size = 2048;
frame_parms->first_carrier_offset = 1412; //2048 - 636
frame_parms->nb_prefix_samples0 = 176;
frame_parms->nb_prefix_samples = 144;
}
break;
case 133:
case 162:
case 189:
case 217: //80 MHz
if (frame_parms->threequarter_fs) {
frame_parms->ofdm_symbol_size = 3072;
frame_parms->first_carrier_offset = 1770; //3072 - 1302
frame_parms->nb_prefix_samples0 = 264;
frame_parms->nb_prefix_samples = 216;
}
else {
frame_parms->ofdm_symbol_size = 4096;
frame_parms->first_carrier_offset = 2794; //4096 - 1302
frame_parms->nb_prefix_samples0 = 352;
frame_parms->nb_prefix_samples = 288;
}
break;
case 245:
case 273:
default:
AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", N_RB, mu, frame_parms);
}
break;
case NR_MU_2: //60kHz scs
frame_parms->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_2];
frame_parms->slots_per_subframe = nr_slots_per_subframe[NR_MU_2];
switch(N_RB){ //FR1 bands only
case 11:
case 18:
case 38:
case 24:
case 31:
case 51:
case 65:
case 79:
case 93:
case 107:
case 121:
case 135:
default:
AssertFatal(1==0,"Number of resource blocks %d undefined for mu %d, frame parms = %p\n", N_RB, mu, frame_parms);
}
break;
case NR_MU_3:
frame_parms->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_3];
frame_parms->slots_per_subframe = nr_slots_per_subframe[NR_MU_3];
break;
case NR_MU_4:
frame_parms->subcarrier_spacing = nr_subcarrier_spacing[NR_MU_4];
frame_parms->slots_per_subframe = nr_slots_per_subframe[NR_MU_4];
break;
default:
AssertFatal(1==0,"Invalid numerology index %d", mu);
}
frame_parms->symbols_per_slot = ((Ncp == NORMAL)? 14 : 12); // to redefine for different slot formats
frame_parms->samples_per_subframe_wCP = frame_parms->ofdm_symbol_size * frame_parms->symbols_per_slot * frame_parms->slots_per_subframe;
frame_parms->samples_per_frame_wCP = 10 * frame_parms->samples_per_subframe_wCP;
frame_parms->samples_per_subframe = (frame_parms->samples_per_subframe_wCP + (frame_parms->nb_prefix_samples0 * frame_parms->slots_per_subframe) +
(frame_parms->nb_prefix_samples * frame_parms->slots_per_subframe * (frame_parms->symbols_per_slot - 1)));
frame_parms->samples_per_frame = 10 * frame_parms->samples_per_subframe;
return 0;
}
int nr_init_frame_parms_ue(nfapi_config_request_t* config,
NR_DL_FRAME_PARMS *frame_parms)
{
int N_RB = 106;
int Ncp = 0;
int mu = 1;
#if DISABLE_LOG_X
printf("Initializing frame parms for mu %d, N_RB %d, Ncp %d\n",mu, N_RB, Ncp);
#else
......@@ -152,11 +277,29 @@ int nr_init_frame_parms(nfapi_config_request_t* config,
AssertFatal(1==0,"Invalid numerology index %d", mu);
}
frame_parms->nb_prefix_samples0 = 160;
frame_parms->nb_prefix_samples = 144;
frame_parms->symbols_per_tti = 14;
frame_parms->numerology_index = 0;
frame_parms->ttis_per_subframe = 1;
frame_parms->slots_per_tti = 2; //only slot config 1 is supported
frame_parms->nb_prefix_samples=(frame_parms->nb_prefix_samples*3)>>2;
frame_parms->nb_prefix_samples0=(frame_parms->nb_prefix_samples0*3)>>2;
frame_parms->ofdm_symbol_size = 2048;
frame_parms->samples_per_tti = 30720;
//#ifdef UE_NR_PHY_DEMO
frame_parms->samples_per_subframe = 30720 * frame_parms->ttis_per_subframe;
//#else
// frame_parms->samples_per_subframe = 30720;
//#endif
frame_parms->first_carrier_offset = 2048-600;
frame_parms->symbols_per_slot = ((Ncp == NORMAL)? 14 : 12); // to redefine for different slot formats
frame_parms->samples_per_subframe_wCP = frame_parms->ofdm_symbol_size * frame_parms->symbols_per_slot * frame_parms->slots_per_subframe;
frame_parms->samples_per_frame_wCP = 10 * frame_parms->samples_per_subframe_wCP;
frame_parms->samples_per_subframe = frame_parms->samples_per_subframe_wCP + (frame_parms->nb_prefix_samples0 * frame_parms->slots_per_subframe) +
(frame_parms->nb_prefix_samples * frame_parms->slots_per_subframe * (frame_parms->symbols_per_slot - 1));
//frame_parms->samples_per_subframe = (frame_parms->samples_per_subframe_wCP + (frame_parms->nb_prefix_samples0 * frame_parms->slots_per_subframe) +
// (frame_parms->nb_prefix_samples * frame_parms->slots_per_subframe * (frame_parms->symbols_per_slot - 1)));
frame_parms->samples_per_frame = 10 * frame_parms->samples_per_subframe;
......
......@@ -375,6 +375,7 @@ void phy_config_request(PHY_Config_t *phy_config);
int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms,uint8_t osf);
void dump_frame_parms(LTE_DL_FRAME_PARMS *frame_parms);
int nr_init_frame_parms(nfapi_config_request_t* config, NR_DL_FRAME_PARMS *frame_parms);
int nr_init_frame_parms_ue(nfapi_config_request_t* config, NR_DL_FRAME_PARMS *frame_parms);
void nr_dump_frame_parms(NR_DL_FRAME_PARMS *frame_parms);
int phy_init_nr_gNB(PHY_VARS_gNB *gNB, unsigned char is_secondary_gNB, unsigned char abstraction_flag);
void nr_phy_config_request(PHY_VARS_gNB *gNB);
......
......@@ -44,6 +44,10 @@
#include "PHY/NR_REFSIG/sss_nr.h"
extern openair0_config_t openair0_cfg[];
static nfapi_config_request_t config_t;
static nfapi_config_request_t* config =&config_t;
/* forward declarations */
void set_default_frame_parms_single(nfapi_config_request_t *config, NR_DL_FRAME_PARMS *frame_parms);
//#define DEBUG_INITIAL_SYNCH
......@@ -196,6 +200,7 @@ int nr_initial_sync(PHY_VARS_NR_UE *ue, runmode_t mode)
NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
int ret=-1;
int aarx,rx_power=0;
//nfapi_config_request_t* config;
/*offset parameters to be updated from higher layer */
k_ssb =0;
......@@ -208,7 +213,8 @@ int nr_initial_sync(PHY_VARS_NR_UE *ue, runmode_t mode)
// First try FDD normal prefix
frame_parms->Ncp=NORMAL;
frame_parms->frame_type=FDD;
init_frame_parms(frame_parms,1);
set_default_frame_parms_single(config,frame_parms);
nr_init_frame_parms_ue(config,frame_parms);
/*
write_output("rxdata0.m","rxd0",ue->common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
exit(-1);
......@@ -248,7 +254,8 @@ int nr_initial_sync(PHY_VARS_NR_UE *ue, runmode_t mode)
rx_sss_nr(ue,&metric_fdd_ncp,&phase_fdd_ncp);
init_frame_parms(&ue->frame_parms,1);
set_default_frame_parms_single(config,&ue->frame_parms);
nr_init_frame_parms_ue(config,&ue->frame_parms);
//generate_dmrs_pbch(ue->dmrs_pbch_bitmap_nr, frame_parms->Nid_cell);
ret = pbch_detection(ue,mode);
// write_output("rxdata2.m","rxd2",ue->common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
......
......@@ -846,14 +846,14 @@ int pss_search_time_nr(int **rxdata, ///rx data in time domain
LOG_I(PHY,"[UE] nr_synchro_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n", pss_source, peak_position, peak_value, dB_fixed(peak_value)/2);
#ifdef DEBUG_PSS_NR
//#ifdef DEBUG_PSS_NR
#define PSS_DETECTION_FLOOR_NR (31)
if ((dB_fixed(peak_value)/2) > PSS_DETECTION_FLOOR_NR) {
printf("[UE] nr_synchro_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n", pss_source, peak_position, peak_value,dB_fixed(peak_value)/2);
}
#endif
//#endif
#ifdef DEBUG_PHY
......
......@@ -589,7 +589,7 @@ int rx_sss_nr(PHY_VARS_NR_UE *ue, int32_t *tot_metric,uint8_t *phase_max)
}
}
#ifdef DEBUG_SSS_NR
//#ifdef DEBUG_SSS_NR
#define SSS_METRIC_FLOOR_NR (30000)
if (*tot_metric > SSS_METRIC_FLOOR_NR) {
......@@ -597,7 +597,7 @@ if (*tot_metric > SSS_METRIC_FLOOR_NR) {
Nid1 = GET_NID1(frame_parms->Nid_cell);
printf("Nid2 %d Nid1 %d tot_metric %d, phase_max %d \n", Nid2, Nid1, *tot_metric, *phase_max);
}
#endif
//#endif
return(0);
}
[AD9371]
ad9371-phy.in_voltage2_rf_port_select = OFF
ad9371-phy.in_voltage2_hardwaregain = -156.000000 dB
ad9371-phy.in_voltage2_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_voltage0_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage0_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage0_quadrature_tracking_en = 1
ad9371-phy.out_voltage1_hardwaregain = 0.000000 dB
ad9371-phy.out_voltage1_lo_leakage_tracking_en = 0
ad9371-phy.out_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage1_TX_LO_frequency = 2560000000
ad9371-phy.out_altvoltage2_RX_SN_LO_frequency = 2680000000
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage0_gain_control_mode = manual
ad9371-phy.in_voltage0_quadrature_tracking_en = 1
ad9371-phy.in_voltage0_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage0_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.in_voltage1_quadrature_tracking_en = 1
ad9371-phy.in_voltage1_hardwaregain = 30.000000 dB
ad9371-phy.in_voltage1_temp_comp_gain = 0.00 dB
ad9371-phy.in_voltage1_gain_control_mode = manual
ad9371-phy.in_voltage_rf_port_select_available = OFF INTERNALCALS OBS_SNIFFER SN_A SN_B SN_C ORX1_TX_LO ORX2_TX_LO ORX1_SN_LO ORX2_SN_LO
ad9371-phy.out_altvoltage0_RX_LO_frequency = 2680000000
ad9371-phy.calibrate_rx_qec_en = 0
ad9371-phy.calibrate_tx_lol_en = 0
ad9371-phy.calibrate_vswr_en = 0
ad9371-phy.calibrate_tx_qec_en = 0
ad9371-phy.calibrate_clgc_en = 0
ad9371-phy.ensm_mode = radio_on
ad9371-phy.calibrate_tx_lol_ext_en = 0
ad9371-phy.calibrate_dpd_en = 0
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage0_TX1_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage5_TX2_I_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage4_TX2_I_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_frequency = 7999809
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage6_TX2_Q_F1_scale = 0.251160
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage3_TX1_Q_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_phase = 0
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_scale = 0.000000
axi-ad9371-tx-hpc.out_altvoltage7_TX2_Q_F2_frequency = 1000327
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_raw = 1
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_phase = 0
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_scale = 0.501160
axi-ad9371-tx-hpc.out_altvoltage2_TX1_Q_F1_frequency = 1999718
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_frequency = 19998117
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_raw = 1
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_phase = 90000
axi-ad9371-tx-hpc.out_altvoltage1_TX1_I_F2_scale = 0.000000
load_myk_profile_file = /targets/ARCH/ADRV9371_ZC706/USERSPACE/PROFILES/profileNR80MHz.txt
dds_mode_tx1 = 1
dds_mode_tx2 = 1
dac_buf_filename = /usr/local/lib/osc/waveforms/LTE20.mat
tx_channel_0 = 1
tx_channel_1 = 1
tx_channel_2 = 0
tx_channel_3 = 0
global_settings_show = 1
tx_show = 1
rx_show = 1
obs_show = 1
fpga_show = 1
[ADRV9371_ZC706]
# NO_DEBUG=0; DEBUG=1
debug_mode = 0
# 20MHz 40MHz 80MHz=1; 10MHz=2; 5MHz=4
interpolation_decimation_factor = 1
# is taken into account only if "ad9371-phy.in_voltage0_gain_control_mode = manual"
rx_gain_offset = 53
......@@ -413,7 +413,7 @@ static void *UE_thread_synch(void *arg) {
//UE->rfdevice.trx_set_gains_func(&openair0,&openair0_cfg[0]);
//UE->rfdevice.trx_stop_func(&UE->rfdevice);
// sleep(1);
//nr_init_frame_parms(&UE->frame_parms);
nr_init_frame_parms_ue(&UE->frame_parms);
/*if (UE->rfdevice.trx_start_func(&UE->rfdevice) != 0 ) {
LOG_E(HW,"Could not start the device\n");
oai_exit=1;
......@@ -733,8 +733,8 @@ void *UE_thread(void *arg) {
#ifdef NAS_UE
MessageDef *message_p;
message_p = itti_alloc_new_message(TASK_NAS_UE, INITIALIZE_MESSAGE);
itti_send_msg_to_task (TASK_NAS_UE, UE->Mod_id + NB_eNB_INST, message_p);
//message_p = itti_alloc_new_message(TASK_NAS_UE, INITIALIZE_MESSAGE);
//itti_send_msg_to_task (TASK_NAS_UE, UE->Mod_id + NB_eNB_INST, message_p);
#endif
int tti_nr=-1;
......
......@@ -693,6 +693,73 @@ int T_dont_fork = 0; /* default is to fork, see 'T_init' to understand */
}
}
void set_default_frame_parms_single(nfapi_config_request_t *config, NR_DL_FRAME_PARMS *frame_parms) {
//int CC_id;
//for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
frame_parms = (NR_DL_FRAME_PARMS*) malloc(sizeof(NR_DL_FRAME_PARMS));
/* Set some default values that may be overwritten while reading options */
frame_parms = (NR_DL_FRAME_PARMS*) malloc(sizeof(NR_DL_FRAME_PARMS));
config = (nfapi_config_request_t*) malloc(sizeof(nfapi_config_request_t));
config->subframe_config.numerology_index_mu.value =1;
config->subframe_config.duplex_mode.value = 1; //FDD
config->subframe_config.dl_cyclic_prefix_type.value = 0; //NORMAL
config->rf_config.dl_channel_bandwidth.value = 106;
config->rf_config.ul_channel_bandwidth.value = 106;
config->rf_config.tx_antenna_ports.value = 1;
config->rf_config.rx_antenna_ports.value = 1;
config->sch_config.physical_cell_id.value = 0;
frame_parms->frame_type = FDD;
frame_parms->tdd_config = 3;
//frame_parms[CC_id]->tdd_config_S = 0;
frame_parms->N_RB_DL = 100;
frame_parms->N_RB_UL = 100;
frame_parms->Ncp = NORMAL;
//frame_parms[CC_id]->Ncp_UL = NORMAL;
frame_parms->Nid_cell = 0;
//frame_parms[CC_id]->num_MBSFN_config = 0;
frame_parms->nb_antenna_ports_eNB = 1;
frame_parms->nb_antennas_tx = 1;
frame_parms->nb_antennas_rx = 1;
//frame_parms[CC_id]->nushift = 0;
///frame_parms[CC_id]->phich_config_common.phich_resource = oneSixth;
//frame_parms[CC_id]->phich_config_common.phich_duration = normal;
// UL RS Config
/*frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift = 1;//n_DMRS1 set to 0
frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1;
frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0;
frame_parms[CC_id]->pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0;
frame_parms[CC_id]->pusch_config_common.n_SB = 1;
frame_parms[CC_id]->pusch_config_common.hoppingMode = 0;
frame_parms[CC_id]->pusch_config_common.pusch_HoppingOffset = 0;
frame_parms[CC_id]->pusch_config_common.enable64QAM = 0;
frame_parms[CC_id]->prach_config_common.rootSequenceIndex=22;
frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=1;
frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_ConfigIndex=0;
frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.highSpeedFlag=0;
frame_parms[CC_id]->prach_config_common.prach_ConfigInfo.prach_FreqOffset=0;*/
// NR: Init to legacy LTE 20Mhz params
frame_parms->numerology_index = 0;
frame_parms->ttis_per_subframe = 1;
frame_parms->slots_per_tti = 2;
downlink_frequency[0][0] = 2680000000; // Use float to avoid issue with frequency over 2^31.
//downlink_frequency[CC_id][1] = downlink_frequency[CC_id][0];
//downlink_frequency[CC_id][2] = downlink_frequency[CC_id][0];
//downlink_frequency[CC_id][3] = downlink_frequency[CC_id][0];
//printf("Downlink for CC_id %d frequency set to %u\n", CC_id, downlink_frequency[CC_id][0]);
//}
}
void init_openair0(void);
void init_openair0() {
......@@ -931,10 +998,10 @@ int main( int argc, char **argv ) {
set_default_frame_parms(config[CC_id],frame_parms[CC_id]);
//init_ul_hopping(frame_parms[CC_id]);
nr_init_frame_parms(config[CC_id],frame_parms[CC_id]);
nr_init_frame_parms_ue(config[CC_id],frame_parms[CC_id]);
printf("after init frame_parms %d\n",frame_parms[CC_id]->ofdm_symbol_size);
// phy_init_top(frame_parms[CC_id]);
//phy_init_lte_top(frame_parms[CC_id]);
phy_init_nr_top(frame_parms[CC_id]);
}
......@@ -1009,8 +1076,10 @@ int main( int argc, char **argv ) {
//UE[CC_id]->pdcch_vars[1][0]->crnti = 0x1235;
}
//UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off;
//UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id];
rx_gain[CC_id][0] = 81;
UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off;
UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id];
if (frame_parms[CC_id]->frame_type==FDD) {
UE[CC_id]->N_TA_offset = 0;
......
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