1. 21 Sep, 2017 2 commits
  2. 19 Sep, 2017 1 commit
  3. 15 Sep, 2017 1 commit
  4. 14 Sep, 2017 1 commit
  5. 17 Aug, 2017 3 commits
  6. 13 Aug, 2017 1 commit
  7. 08 Aug, 2017 1 commit
    • knopp's avatar
      L1/L2 scheduling extensions for BL/CE operation, BR random-access procedure,... · ad98f5aa
      knopp authored
      L1/L2 scheduling extensions for BL/CE operation, BR random-access procedure, BR PRACH detection. Still untested, but compilation succeeds. Missing elements in L2 - PUSCH programming for Msg3, Msg4 retransmission programming for BL/CE. DLSCH/ULSCH programming for UE-specific DLSCH/ULSCH for BL/CE
      ad98f5aa
  8. 25 Jul, 2017 2 commits
  9. 24 Jul, 2017 1 commit
  10. 19 Jul, 2017 1 commit
  11. 06 Jul, 2017 1 commit
  12. 04 Jun, 2017 1 commit
  13. 19 May, 2017 4 commits
  14. 18 May, 2017 2 commits
  15. 15 May, 2017 2 commits
  16. 12 May, 2017 1 commit
    • Gabriel's avatar
      bug fixes from Fujitsu (bug 37) · ad6d0ac5
      Gabriel authored
      ```-------------------------------------------------------
      bug 37
      
      Ttile:
      Sending side is as follows.
      rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
      So, 2 bit shift looks correct.
      
      Bug Location:
      ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
      ```
      
      -------------------------------------------------------
      ad6d0ac5
  17. 03 May, 2017 3 commits
  18. 02 May, 2017 1 commit
  19. 26 Apr, 2017 1 commit
  20. 25 Apr, 2017 4 commits
  21. 24 Apr, 2017 2 commits
  22. 21 Apr, 2017 1 commit
  23. 18 Apr, 2017 1 commit
  24. 17 Apr, 2017 1 commit
  25. 14 Apr, 2017 1 commit
    • Cedric Roux's avatar
      hotfix: fix TDD 20MHz DCI0 structure · 20a2bfd1
      Cedric Roux authored
      In 20MHz the UE didn't do any uplink granted by DCI0.
      It was replying to RAR, so uplink decoding was okay.
      
      Turns out the DCI0 structure for TDD was wrong.
      20a2bfd1