Commit c4b7d4c1 authored by knopp's avatar knopp

updates to UL (DFTs for 10/20 MHz), Ndi toggling, DCI structures

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4600 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 21635af2
......@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) {
k++;k2++;k2++;
}
}
if (ND>0)
d[2] = LTE_NULL;//d[(3*D)+2];
// if (ND>0)
// d[2] = LTE_NULL;//d[(3*D)+2];
}
......@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC,
k=0;
for (;(ind<Ncb)&&(k<E);ind++) {
e2[k]=w[ind];
// e2[k]=w[ind];
#ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif
if (w[ind] != LTE_NULL) k++;
if (w[ind] != LTE_NULL) e2[k++]=w[ind];
}
while(k<E) {
for (ind=0;(ind<Ncb)&&(k<E);ind++) {
e2[k] = w[ind];
// e2[k] = w[ind];
#ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif
if (w[ind] != LTE_NULL) k++;
if (w[ind] != LTE_NULL) e2[k++]=w[ind];
}
}
/*
......
......@@ -1963,7 +1963,7 @@ u8 get_num_pdcch_symbols(u8 num_dci,
// compute numCCE
for (i=0;i<num_dci;i++) {
// printf("dci %d => %d\n",i,dci_alloc[i].L);
// printf("dci %d => %d\n",i,dci_alloc[i].L);
numCCE += (1<<(dci_alloc[i].L));
}
......@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mod_sym_t *y[2];
mod_sym_t *wbar[2];
#ifdef IFFT_FPGA
u8 qpsk_table_offset = 0;
u8 qpsk_table_offset2 = 0;
#endif
int nushiftmod3 = frame_parms->nushift%3;
int Msymb2;
......@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr = e;
if (frame_parms->mode1_flag) { //SISO
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i++) {
//((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
//((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
......@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr++;
}
#else
for (i=0;i<Msymb2;i++) {
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET;
if (*e_ptr == 1)
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1)
qpsk_table_offset+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset;
y[1][i] = (mod_sym_t) qpsk_table_offset;
}
#endif
}
else { //ALAMOUTI
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
......@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1];
}
#else
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
LOG_I(PHY," PDCCH Modulation: Symbol %d : REG %d/%d\n",i,i>>2,Msymb2>>2);
#endif
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //x0
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x0*
if (*e_ptr == 1) { //real
qpsk_table_offset+=2;
qpsk_table_offset2+=2;
}
e_ptr++;
if (*e_ptr == 1) //imag
qpsk_table_offset+=1;
else
qpsk_table_offset2+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset; // x0
y[1][i+1] = (mod_sym_t) qpsk_table_offset2; // x0*
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //-x1*
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x1
if (*e_ptr == 1) // flipping bit for real part of symbol means taking -x1*
qpsk_table_offset2+=2;
else
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1) {
qpsk_table_offset+=1;
qpsk_table_offset2+=1;
}
e_ptr++;
y[1][i] = (mod_sym_t) qpsk_table_offset; // -x1*
y[0][i+1] = (mod_sym_t) qpsk_table_offset2; // x1
}
#endif
}
......@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mprime=0;
nsymb = (frame_parms->Ncp==0) ? 14:12;
#ifdef IFFT_FPGA
re_offset = frame_parms->N_RB_DL*12/2;
#else
re_offset = frame_parms->first_carrier_offset;
#endif
// This is the REG allocation algorithm from 36-211, second part of Section 6.8.5
// printf("DCI : txdataF %p (0 %p)\n",&txdataF[0][512*14*subframe],&txdataF[0][0]);
// printf("DCI (SF %d) : txdataF %p (0 %p)\n",subframe,&txdataF[0][512*14*subframe],&txdataF[0][0]);
for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) {
for (lprime=0;lprime<num_pdcch_symbols;lprime++) {
#ifdef IFFT_FPGA
symbol_offset = (u32)frame_parms->N_RB_DL*12*(lprime+(subframe*nsymb));
#else
symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb));
#endif
......@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
} //lprime loop
re_offset++;
#ifdef IFFT_FPGA
if (re_offset == (frame_parms->N_RB_DL*12))
re_offset = 0;
#else
if (re_offset == (frame_parms->ofdm_symbol_size))
re_offset = 1;
#endif
} // kprime loop
return(num_pdcch_symbols);
}
......
......@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t;
/// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits)
struct DCI1A_1_5MHz_TDD_1_6 {
/// padding
uint32_t padding:8;
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:9;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t;
/// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits)
struct DCI1A_10MHz_TDD_1_6 {
/// padding
uint32_t padding:2;
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:3;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t;
struct DCI0_20MHz_TDD_1_6 {
/// Padding
uint32_t padding:2;
/// CQI Request
/// CQI request
uint32_t cqi_req:1;
/// DAI
uint32_t dai:2;
......@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t;
/// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits)
struct DCI1A_20MHz_TDD_1_6 {
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:1;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t;
struct DCI1A_1_5MHz_FDD {
/// padding
uint32_t padding:11;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:12;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t;
struct DCI1A_5MHz_FDD {
/// padding
uint32_t padding:7;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:8;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t;
struct DCI1A_10MHz_FDD {
/// padding
uint32_t padding:5;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:6;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t;
struct DCI1A_20MHz_FDD {
/// padding
uint32_t padding:3;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:4;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......
This diff is collapsed.
......@@ -88,8 +88,6 @@ typedef enum {
typedef struct {
/// Flag indicating that this DLSCH is active (i.e. not the first round)
uint8_t Ndi;
/// Status Flag indicating for this DLSCH (idle,active,disabled)
SCH_status_t status;
/// Transport block size
......@@ -131,8 +129,12 @@ typedef struct {
} LTE_DL_eNB_HARQ_t;
typedef struct {
/// Indicator of first transmission
uint8_t first_tx;
/// Last Ndi received for this process on DCI (used for C-RNTI only)
uint8_t DCINdi;
/// Flag indicating that this ULSCH has a new packet (start of new round)
uint8_t Ndi;
// uint8_t Ndi;
/// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
......@@ -325,8 +327,6 @@ typedef struct {
uint8_t dci_alloc;
/// Flag indicating that this ULSCH has been allocated by a RAR (otherwise it is a retransmission based on PHICH NAK or DCI)
uint8_t rar_alloc;
/// Flag indicating that this ULSCH has new data
uint8_t Ndi;
/// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
......@@ -463,8 +463,10 @@ typedef struct {
} LTE_eNB_ULSCH_t;
typedef struct {
/// Flag indicating that this DLSCH has a new transport block
uint8_t Ndi;
/// Indicator of first transmission
uint8_t first_tx;
/// Last Ndi received for this process on DCI (used for C-RNTI only)
uint8_t DCINdi;
/// DLSCH status flag indicating
SCH_status_t status;
/// Transport block size
......
......@@ -141,6 +141,7 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,unsigne
MAX_DLSCH_PAYLOAD_BYTES/bw_scaling,bw_scaling, i,dlsch->harq_processes[i]);
if (dlsch->harq_processes[i]) {
bzero(dlsch->harq_processes[i],sizeof(LTE_DL_eNB_HARQ_t));
// dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (unsigned char*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b) {
bzero(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
......@@ -202,7 +203,7 @@ void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch, u8 abstraction_flag) {
for (i=0;i<Mdlharq;i++) {
if (dlsch->harq_processes[i]) {
dlsch->harq_processes[i]->Ndi = 0;
// dlsch->harq_processes[i]->Ndi = 0;
dlsch->harq_processes[i]->status = 0;
dlsch->harq_processes[i]->round = 0;
if (abstraction_flag==0) {
......@@ -245,7 +246,8 @@ int dlsch_encoding(unsigned char *a,
G = get_G(frame_parms,nb_rb,dlsch->rb_alloc,mod_order,num_pdcch_symbols,frame,subframe);
if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet
// if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet
if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet
/*
int i;
......@@ -382,7 +384,8 @@ void dlsch_encoding_emul(PHY_VARS_eNB *phy_vars_eNB,
unsigned char harq_pid = dlsch->current_harq_pid;
unsigned short i;
if (dlsch->harq_processes[harq_pid]->Ndi == 1) {
// if (dlsch->harq_processes[harq_pid]->Ndi == 1) {
if (dlsch->harq_processes[harq_pid]->round == 0) {
memcpy(dlsch->harq_processes[harq_pid]->b,
DLSCH_pdu,
dlsch->harq_processes[harq_pid]->TBS>>3);
......
......@@ -111,6 +111,7 @@ LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_ite
dlsch->harq_processes[i] = (LTE_DL_UE_HARQ_t *)malloc16(sizeof(LTE_DL_UE_HARQ_t));
if (dlsch->harq_processes[i]) {
memset(dlsch->harq_processes[i],0,sizeof(LTE_DL_UE_HARQ_t));
dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b)
memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
......@@ -235,7 +236,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
// msg("DLSCH Decoding, harq_pid %d Ndi %d\n",harq_pid,harq_process->Ndi);
if (harq_process->Ndi == 1) {
if (harq_process->round == 0) {
// This is a new packet, so compute quantities regarding segmentation
harq_process->B = A+24;
lte_segmentation(NULL,
......@@ -309,7 +310,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
dlsch->Mdlharq,
dlsch->Kmimo,
harq_process->rvidx,
harq_process->Ndi,
(harq_process->round==0)?1:0,
get_Qm(harq_process->mcs),
harq_process->Nl,
r,
......@@ -718,7 +719,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue,
dlsch_ue->harq_ack[subframe].ack = 1;
dlsch_ue->harq_ack[subframe].harq_id = harq_pid;
dlsch_ue->harq_ack[subframe].send_harq_status = 1;
if (dlsch_ue->harq_processes[harq_pid]->Ndi == 1)
if (dlsch_ue->harq_processes[harq_pid]->round == 0)
memcpy(dlsch_ue->harq_processes[harq_pid]->b,
dlsch_eNB->harq_processes[harq_pid]->b,
dlsch_ue->harq_processes[harq_pid]->TBS>>3);
......@@ -746,7 +747,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue,
dlsch_ue->harq_ack[subframe].ack = 1;
dlsch_ue->harq_ack[subframe].harq_id = harq_pid;
dlsch_ue->harq_ack[subframe].send_harq_status = 1;
if (dlsch_ue->harq_processes[harq_pid]->Ndi == 1)
if (dlsch_ue->harq_processes[harq_pid]->round == 0)
memcpy(dlsch_eNB->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->TBS>>3);
break;
default:
......
......@@ -1258,7 +1258,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue,
&phy_vars_ue->ulsch_ue_Msg3_frame[eNB_id],
&phy_vars_ue->ulsch_ue_Msg3_subframe[eNB_id]);
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch->harq_processes[harq_pid]->Ndi = 0;
// ulsch->harq_processes[harq_pid]->Ndi = 0;
ulsch->harq_processes[harq_pid]->round++;
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
if (ulsch->harq_processes[harq_pid]->round>=phy_vars_ue->lte_frame_parms.maxHARQ_Msg3Tx) {
......@@ -1279,7 +1279,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue,
ngroup_PHICH);
//#endif
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch->harq_processes[harq_pid]->Ndi = 0;
// ulsch->harq_processes[harq_pid]->Ndi = 0;
ulsch->harq_processes[harq_pid]->round++;
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
}
......@@ -1400,7 +1400,7 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB,
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH ACK / (no format0 DCI) Setting subframe_scheduling_flag\n",
phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->frame,subframe);
ulsch_eNB[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch_eNB[UE_id]->harq_processes[harq_pid]->Ndi = 0;
// ulsch_eNB[UE_id]->harq_processes[harq_pid]->Ndi = 0;
// ulsch_eNB[UE_id]->harq_processes[harq_pid]->round++; //this is already done in phy_procedures
ulsch_eNB[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch_eNB[UE_id]->harq_processes[harq_pid]->round&3];
}
......
......@@ -62,13 +62,8 @@ void generate_pilots(PHY_VARS_eNB *phy_vars_eNB,
#ifdef IFFT_FPGA
tti_offset = tti*frame_parms->N_RB_DL*12*Nsymb;
samples_per_symbol = frame_parms->N_RB_DL*12;
#else
tti_offset = tti*frame_parms->ofdm_symbol_size*Nsymb;
samples_per_symbol = frame_parms->ofdm_symbol_size;
#endif
slot_offset = (tti*2)%20;
// printf("tti %d : offset %d (slot %d)\n",tti,tti_offset,slot_offset);
......@@ -191,13 +186,8 @@ int generate_pilots_slot(PHY_VARS_eNB *phy_vars_eNB,
second_pilot = (frame_parms->Ncp==0)?4:3;
#ifdef IFFT_FPGA
slot_offset = slot*frame_parms->N_RB_DL*12*Nsymb;
samples_per_symbol = frame_parms->N_RB_DL*12;
#else
slot_offset = slot*frame_parms->ofdm_symbol_size*Nsymb;
samples_per_symbol = frame_parms->ofdm_symbol_size;
#endif
// printf("tti %d : offset %d (slot %d)\n",tti,tti_offset,slot_offset);
//Generate Pilots
......
......@@ -149,7 +149,7 @@ void fill_eNB_dlsch_MCH(PHY_VARS_eNB *phy_vars_eNB,int mcs,int ndi,int rvidx) {
LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->lte_frame_parms;
dlsch->harq_processes[0]->mcs = mcs;
dlsch->harq_processes[0]->Ndi = ndi;
// dlsch->harq_processes[0]->Ndi = ndi;
dlsch->harq_processes[0]->rvidx = rvidx;
dlsch->harq_processes[0]->Nl = 1;
dlsch->harq_processes[0]->TBS = TBStable[get_I_TBS(dlsch->harq_processes[0]->mcs)][frame_parms->N_RB_DL-1];
......@@ -183,7 +183,7 @@ void fill_UE_dlsch_MCH(PHY_VARS_UE *phy_vars_ue,int mcs,int ndi,int rvidx,int eN
dlsch->harq_processes[0]->mcs = mcs;
dlsch->harq_processes[0]->rvidx = rvidx;
dlsch->harq_processes[0]->Ndi = ndi;
// dlsch->harq_processes[0]->Ndi = ndi;
dlsch->harq_processes[0]->Nl = 1;
dlsch->harq_processes[0]->TBS = TBStable[get_I_TBS(dlsch->harq_processes[0]->mcs)][frame_parms->N_RB_DL-1];
dlsch->current_harq_pid = 0;
......
......@@ -111,7 +111,7 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
ulsch->harq_processes[harq_pid]->rar_alloc = 1;
ulsch->harq_processes[harq_pid]->first_rb = RIV2first_rb_LUT[rballoc];
ulsch->harq_processes[harq_pid]->nb_rb = RIV2nb_rb_LUT[rballoc];
ulsch->harq_processes[harq_pid]->Ndi = 1;
// ulsch->harq_processes[harq_pid]->Ndi = 1;
cqireq = rar[3]&1;
if (cqireq==1){
......@@ -133,7 +133,7 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
ulsch->Nsymb_pusch = 12-(frame_parms->Ncp<<1);
ulsch->rnti = (((uint16_t)rar[4])<<8)+rar[5];
if (ulsch->harq_processes[harq_pid]->Ndi == 1) {
if (ulsch->harq_processes[harq_pid]->round == 0) {
ulsch->harq_processes[harq_pid]->status = ACTIVE;
ulsch->harq_processes[harq_pid]->rvidx = 0;
ulsch->harq_processes[harq_pid]->mcs = ((rar[2]&1)<<3)|(rar[3]>>5);
......@@ -152,7 +152,7 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
msg("ulsch ra (eNB): NBRB %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
msg("ulsch ra (eNB): rballoc %x\n",ulsch->harq_processes[harq_pid]->first_rb);
msg("ulsch ra (eNB): harq_pid %d\n",harq_pid);
msg("ulsch ra (eNB): Ndi %d\n",ulsch->harq_processes[harq_pid]->Ndi);
msg("ulsch ra (eNB): round %d\n",ulsch->harq_processes[harq_pid]->round);
msg("ulsch ra (eNB): TBS %d\n",ulsch->harq_processes[harq_pid]->TBS);
msg("ulsch ra (eNB): mcs %d\n",ulsch->harq_processes[harq_pid]->mcs);
msg("ulsch ra (eNB): Or1 %d\n",ulsch->Or1);
......@@ -176,14 +176,14 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *phy_vars_ue,
// int current_dlsch_cqi = phy_vars_ue->current_dlsch_cqi[eNB_id];
uint8_t *rar = (uint8_t *)(rar_pdu+1);
uint8_t harq_pid = subframe2harq_pid(frame_parms,phy_vars_ue->frame,subframe);
uint8_t harq_pid = subframe2harq_pid(frame_parms,((subframe==0)?1:0) + phy_vars_ue->frame,subframe);
uint16_t rballoc;
uint8_t cqireq;
double sinr_eff;
uint16_t *RIV2nb_rb_LUT, *RIV2first_rb_LUT;
uint16_t RIV_max;
LOG_D(PHY,"[eNB][RAPROC] generate_ue_ulsch_params_from_rar: subframe %d (harq_pid %d)\n",subframe,harq_pid);
LOG_D(PHY,"[eNB][RAPROC] Frame %d: generate_ue_ulsch_params_from_rar: subframe %d (harq_pid %d)\n",phy_vars_ue->frame,subframe,harq_pid);
switch (frame_parms->N_RB_DL) {
case 6:
......@@ -232,8 +232,8 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *phy_vars_ue,
return(-1);
}
ulsch->harq_processes[harq_pid]->Ndi = 1;
if (ulsch->harq_processes[harq_pid]->Ndi == 1)
// ulsch->harq_processes[harq_pid]->Ndi = 1;
if (ulsch->harq_processes[harq_pid]->round == 0)
ulsch->harq_processes[harq_pid]->status = ACTIVE;
if (cqireq==1) {
......@@ -275,7 +275,7 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *phy_vars_ue,
ulsch->Nsymb_pusch = 12-(frame_parms->Ncp<<1);
ulsch->rnti = (((uint16_t)rar[4])<<8)+rar[5]; //rar->t_crnti;
if (ulsch->harq_processes[harq_pid]->Ndi == 1) {
if (ulsch->harq_processes[harq_pid]->round == 0) {
ulsch->harq_processes[harq_pid]->status = ACTIVE;
ulsch->harq_processes[harq_pid]->rvidx = 0;
ulsch->harq_processes[harq_pid]->mcs = ((rar[2]&1)<<3)|(rar[3]>>5);
......@@ -300,10 +300,11 @@ int generate_ue_ulsch_params_from_rar(PHY_VARS_UE *phy_vars_ue,
//#ifdef DEBUG_RAR
msg("ulsch ra (UE): harq_pid %d\n",harq_pid);
msg("ulsch ra (UE): NBRB %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
msg("ulsch ra (UE): first_rb %x\n",ulsch->harq_processes[harq_pid]->first_rb);
msg("ulsch ra (UE): nb_rb %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
msg("ulsch ra (UE): Ndi %d\n",ulsch->harq_processes[harq_pid]->Ndi);
msg("ulsch ra (UE): round %d\n",ulsch->harq_processes[harq_pid]->round);
msg("ulsch ra (UE): TBS %d\n",ulsch->harq_processes[harq_pid]->TBS);
msg("ulsch ra (UE): mcs %d\n",ulsch->harq_processes[harq_pid]->mcs);
msg("ulsch ra (UE): TPC %d\n",ulsch->harq_processes[harq_pid]->TPC);
......
......@@ -287,18 +287,18 @@ u32 ulsch_encoding(u8 *a,
ulsch->harq_processes[harq_pid]->control_only = 0;
#ifdef DEBUG_ULSCH_CODING
msg("[PHY][UE] ULSCH coding : A %d, Qm %d, mcs %d, harq_pid %d, Ndi %d, RV %d\n",
msg("[PHY][UE] ULSCH coding : A %d, Qm %d, mcs %d, harq_pid %d, round %d, RV %d\n",
ulsch->harq_processes[harq_pid]->TBS,
Q_m,
ulsch->harq_processes[harq_pid]->mcs,
harq_pid,
ulsch->harq_processes[harq_pid]->Ndi,
ulsch->harq_processes[harq_pid]->round,
ulsch->harq_processes[harq_pid]->rvidx);
for (i=0;i<ulsch->harq_processes[harq_pid]->O_ACK;i++)
msg("ulsch_coding: O_ACK[%d] %d\n",i,ulsch->o_ACK[i]);
msg("ulsch_coding: o_ACK[%d] %d\n",i,ulsch->o_ACK[i]);
for (i=0;i<ulsch->O_RI;i++)
msg("ulsch_coding: O_RI[%d] %d\n",i,ulsch->o_RI[i]);
msg("ulsch_coding: o_RI[%d] %d\n",i,ulsch->o_RI[i]);
msg("ulsch_coding: O=%d\n",ulsch->O);
for (i=0;i<1+((8+ulsch->O)/8);i++) {
......@@ -311,7 +311,7 @@ u32 ulsch_encoding(u8 *a,
print_CQI(ulsch->o,HLC_subband_cqi_rank1_2A,0);
#endif
if (ulsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet
if (ulsch->harq_processes[harq_pid]->round == 0) { // this is a new packet
start_meas(seg_stats);
// Add 24-bit crc (polynomial A) to payload
......
......@@ -174,7 +174,7 @@ void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch, uint8_t abstraction_flag) {
ulsch->rnti = 0;
for (i=0;i<Mdlharq;i++) {
if (ulsch->harq_processes[i]) {
ulsch->harq_processes[i]->Ndi = 0;
// ulsch->harq_processes[i]->Ndi = 0;
ulsch->harq_processes[i]->status = 0;
ulsch->harq_processes[i]->subframe_scheduling_flag = 0;
//ulsch->harq_processes[i]->phich_active = 0; //this will be done later after transmission of PHICH
......@@ -294,9 +294,9 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
#ifdef DEBUG_ULSCH_DECODING
LOG_D(PHY,"ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): Ndi %d, RV %d, mcs %d, O_RI %d, O_ACK %d, G %d, subframe %d\n",
LOG_D(PHY,"ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): round %d, RV %d, mcs %d, O_RI %d, O_ACK %d, G %d, subframe %d\n",
frame_parms->Nid_cell,ulsch->rnti,x2,
ulsch->harq_processes[harq_pid]->Ndi,
ulsch->harq_processes[harq_pid]->round,
ulsch->harq_processes[harq_pid]->rvidx,
ulsch->harq_processes[harq_pid]->mcs,
ulsch->O_RI,
......@@ -305,7 +305,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
subframe);
#endif
if (ulsch->harq_processes[harq_pid]->Ndi == 1) {
if (ulsch->harq_processes[harq_pid]->round == 0) {
// This is a new packet, so compute quantities regarding segmentation
ulsch->harq_processes[harq_pid]->B = A+24;
lte_segmentation(NULL,
......@@ -331,10 +331,10 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
}
if (sumKr==0) {
LOG_N(PHY,"[eNB %d] ulsch_decoding.c: FATAL sumKr is 0!\n",phy_vars_eNB->Mod_id);
LOG_D(PHY,"ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): harq_pid %d Ndi %d, RV %d, mcs %d, O_RI %d, O_ACK %d, G %d, subframe %d\n",
LOG_D(PHY,"ulsch_decoding (Nid_cell %d, rnti %x, x2 %x): harq_pid %d round %d, RV %d, mcs %d, O_RI %d, O_ACK %d, G %d, subframe %d\n",
frame_parms->Nid_cell,ulsch->rnti,x2,
harq_pid,
ulsch->harq_processes[harq_pid]->Ndi,
ulsch->harq_processes[harq_pid]->round,
ulsch->harq_processes[harq_pid]->rvidx,
ulsch->harq_processes[harq_pid]->mcs,
ulsch->O_RI,
......@@ -407,7 +407,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
Q_CQI = Q_m * Qprime;
#ifdef DEBUG_ULSCH_DECODING
printf("ulsch_decoding.c: G %d, Q_RI %d, Q_CQI %d (L %d, Or1 %d)\n",G,Q_RI,Q_CQI,L,ulsch->Or1);
printf("ulsch_decoding.c: G %d, Q_RI %d, Q_CQI %d (L %d, Or1 %d) O_ACK %d\n",G,Q_RI,Q_CQI,L,ulsch->Or1,ulsch->harq_processes[harq_pid]->O_ACK);
#endif
Qprime_CQI = Qprime;
......@@ -768,7 +768,8 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
if (y[q+(Q_m*((r*Cmux) + columnset[j]))]!=0)
ulsch->q_ACK[(q+(Q_m*i))%len_ACK] += y[q+(Q_m*((r*Cmux) + columnset[j]))];
#ifdef DEBUG_ULSCH_DECODING
LOG_D(PHY,"ACK %d => %d (%d,%d,%d)\n",(q+(Q_m*i))%len_ACK,ulsch->q_ACK[(q+(Q_m*i))%len_ACK],q+(Q_m*((r*Cmux) + columnset[j])),r,columnset[j]);
// LOG_D(PHY,"ACK %d => %d (%d,%d,%d)\n",(q+(Q_m*i))%len_ACK,ulsch->q_ACK[(q+(Q_m*i))%len_ACK],q+(Q_m*((r*Cmux) + columnset[j])),r,columnset[j]);
printf("ACK %d => %d (%d,%d,%d)\n",(q+(Q_m*i))%len_ACK,ulsch->q_ACK[(q+(Q_m*i))%len_ACK],q+(Q_m*((r*Cmux) + columnset[j])),r,columnset[j]);
#endif
y[q+(Q_m*((r*Cmux) + columnset[j]))]=0; // NULL LLRs in ACK positions
}
......@@ -874,6 +875,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
#endif
}
// write_output("/tmp/ulsch_e.m","ulsch_e",ulsch->e,iprime,1,0);
break;
case 4:
for (iprime=0;iprime<(Hprime-Qprime_CQI)<<2;) {
......@@ -1161,7 +1163,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
ulsch->Mdlharq,
1,
ulsch->harq_processes[harq_pid]->rvidx,
ulsch->harq_processes[harq_pid]->Ndi,
(ulsch->harq_processes[harq_pid]->round==0)?1:0, // clear
get_Qm_ul(ulsch->harq_processes[harq_pid]->mcs),
1,
r,
......@@ -1181,14 +1183,14 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *phy_vars_eNB,
&ulsch->harq_processes[harq_pid]->d[r][96],
ulsch->harq_processes[harq_pid]->w[r]);
stop_meas(&phy_vars_eNB->ulsch_deinterleaving_stats);
/*
#ifdef DEBUG_ULSCH_DECODING
msg("decoder input(segment %d) :",r);
for (i=0;i<(3*8*Kr_bytes)+12;i++)
msg("%d : %d\n",i,ulsch->harq_processes[harq_pid]->d[r][96+i]);
msg("\n");
#endif
*/
}
#ifdef OMP
......
<
......@@ -247,14 +247,94 @@ void lte_idft(LTE_DL_FRAME_PARMS *frame_parms,uint32_t *z, uint16_t Msc_PUSCH) {
break;
case 288:
dft288(idft_in0,idft_out0,1);
dft288(idft_in1,idft_out1,1);
dft288(idft_in1,idft_out1,1);
dft288(idft_in2,idft_out2,1);
break;
case 300:
case 300:
dft300(idft_in0,idft_out0,1);
dft300(idft_in1,idft_out1,1);
dft300(idft_in2,idft_out2,1);
break;
case 324:
dft324((int16_t*)idft_in0,(int16_t*)idft_out0,1);
dft324((int16_t*)idft_in1,(int16_t*)idft_out1,1);
dft324((int16_t*)idft_in2,(int16_t*)idft_out2,1);
break;
case 360:
dft360((int16_t*)idft_in0,(int16_t*)idft_out0,1);
dft360((int16_t*)idft_in1,(int16_t*)idft_out1,1);
dft360((int16_t*)idft_in2,(int16_t*)idft_out2,1);
break;
case 384:
dft384((int16_t*)idft_in0,(int16_t*)idft_out0,1);
dft384((int16_t*)idft_in1,(int16_t*)idft_out1,1);
dft384((int16_t*)idft_in2,(int16_t*)idft_out2,1);
break;
case 432:
dft432((int16_t*)idft_in0,(int16_t*)idft_out0,1);
dft432((int16_t*)idft_in1,(int16_t*)idft_out1,1);
dft432((int16_t*)idft_in2,(int16_t*)idft_out2,1);