Commit 90e6a90e authored by knopp's avatar knopp
Browse files

commit prior to merge

parent 5eb919e9
......@@ -2574,7 +2574,7 @@ add_executable(nr_dlsim
${OPENAIR_DIR}/common/utils/backtrace.c
${OPENAIR_DIR}/common/utils/system.c
${T_SOURCE})
target_link_libraries(nr_dlsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl)
target_link_libraries(nr_dlsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON MAC_NR RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl)
add_executable(nr_prachsim
${OPENAIR1_DIR}/SIMULATION/NR_PHY/prachsim.c
......
......@@ -51,8 +51,8 @@
#define FAPI_NR_UL_CONFIG_LIST_NUM 10
#define FAPI_NR_UL_CONFIG_TYPE_PRACH 0x01
#define FAPI_NR_UL_CONFIG_TYPE_PUCCH 0x02
#define FAPI_NR_UL_CONFIG_TYPE_PUSCH 0x03
#define FAPI_NR_UL_CONFIG_TYPE_UCI 0x02
#define FAPI_NR_UL_CONFIG_TYPE_ULSCH 0x03
#define FAPI_NR_UL_CONFIG_TYPE_SRS 0x04
......
......@@ -197,11 +197,11 @@ typedef struct {
} fapi_nr_rx_indication_body_t;
///
#define NFAPI_RX_IND_MAX_PDU 100
#define FAPI_RX_IND_MAX_PDU 100
typedef struct {
uint32_t sfn_slot;
uint16_t number_pdus;
fapi_nr_rx_indication_body_t rx_indication_body[NFAPI_RX_IND_MAX_PDU];
fapi_nr_rx_indication_body_t rx_indication_body[FAPI_RX_IND_MAX_PDU];
} fapi_nr_rx_indication_t;
typedef struct {
......@@ -224,22 +224,22 @@ typedef struct {
fapi_nr_tx_request_body_t *tx_request_body;
} fapi_nr_tx_request_t;
typedef struct {
uint8_t preamble_index;
uint8_t prach_configuration_index;
uint16_t preamble_length;
uint8_t power_ramping_step;
uint16_t preamble_received_target_power;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t subcarrier_spacing;
uint8_t restrictedset_config;
uint16_t root_sequence_index;
uint16_t rsrp_threshold_ssb;
uint16_t rsrp_threshold_sul;
uint16_t prach_freq_offset;
} fapi_nr_ul_config_prach_pdu;
typedef struct {
uint8_t preamble_index;
uint8_t prach_configuration_index;
uint16_t preamble_length;
uint8_t power_ramping_step;
uint16_t preamble_received_target_power;
uint8_t msg1_fdm;
uint8_t msg1_frequency_start;
uint8_t zero_correlation_zone_config;
uint8_t subcarrier_spacing;
uint8_t restrictedset_config;
uint16_t root_sequence_index;
uint16_t rsrp_threshold_ssb;
uint16_t rsrp_threshold_sul;
uint16_t prach_freq_offset;
} fapi_nr_ul_config_prach_pdu;
typedef struct {
......@@ -322,7 +322,7 @@ typedef struct {
// pathlossReferenceRSs SEQUENCE (SIZE (1..maxNrofPUCCH-PathlossReferenceRSs)) OF PUCCH-PathlossReferenceRS OPTIONAL, -- Need M
int8_t twoPUCCH_PC_AdjustmentStates;
} fapi_nr_ul_config_pucch_pdu;
} fapi_nr_ul_config_uci_pdu;
typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t;
typedef struct{
......@@ -352,23 +352,39 @@ typedef struct {
uint8_t maxCodeBlockGroupsPerTransportBlock;
uint8_t ptrs_dmrs_association_port;
uint8_t beta_offset_ind;
} fapi_nr_ul_config_pusch_pdu_rel15_t;
} fapi_nr_ul_config_ulsch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
fapi_nr_ul_config_pusch_pdu_rel15_t ulsch_pdu_rel15;
} fapi_nr_ul_config_pusch_pdu;
fapi_nr_ul_config_ulsch_pdu_rel15_t ulsch_pdu_rel15;
} fapi_nr_ul_config_ulsch_pdu;
typedef struct {
} fapi_nr_ul_config_srs_pdu;
// nFAPI enums
typedef enum {
FAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
FAPI_NR_DL_CONFIG_BCH_PDU_TYPE,
FAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE,
FAPI_NR_DL_CONFIG_PCH_PDU_TYPE,
} fapi_nr_dl_config_pdu_type_e;
// nFAPI enums
typedef enum {
FAPI_NR_UL_CONFIG_PRACH_PDU_TYPE = 0,
FAPI_NR_UL_CONFIG_ULSCH_PDU_TYPE,
FAPI_NR_UL_CONFIG_UCI_PDU_TYPE,
FAPI_NR_UL_CONFIG_SRS_PDU_TYPE,
} fapi_nr_ul_config_pdu_type_e;
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_ul_config_prach_pdu prach_config_pdu;
fapi_nr_ul_config_pucch_pdu pucch_config_pdu;
fapi_nr_ul_config_pusch_pdu ulsch_config_pdu;
fapi_nr_ul_config_uci_pdu uci_config_pdu;
fapi_nr_ul_config_ulsch_pdu ulsch_config_pdu;
fapi_nr_ul_config_srs_pdu srs_config_pdu;
};
} fapi_nr_ul_config_request_pdu_t;
......@@ -436,6 +452,20 @@ typedef struct {
// to be check the fields needed to L1 with NR_DL_UE_HARQ_t and NR_UE_DLSCH_t
} fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint8_t subcarrier_spacing_common;
uint8_t ssb_subcarrier_offset;
uint8_t dmrs_type_a_position;
uint8_t pdcch_config_sib1;
uint8_t cell_barred;
uint8_t intra_frequency_reselection;
uint16_t system_frame_number;
uint8_t ssb_index;
uint8_t half_frame_bit;
} fapi_nr_dl_config_bch_pdu;
typedef struct {
uint16_t rnti;
fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_rel15;
......@@ -444,6 +474,7 @@ typedef struct {
typedef struct {
uint8_t pdu_type;
union {
fapi_nr_dl_config_bch_pdu bch_config_pdu;
fapi_nr_dl_config_dci_pdu dci_config_pdu;
fapi_nr_dl_config_dlsch_pdu dlsch_config_pdu;
};
......@@ -461,6 +492,154 @@ typedef struct {
//
typedef struct {
uint8_t numerology_index_mu;
uint8_t duplex_mode;
uint8_t dl_cyclic_prefix_type;
uint8_t ul_cyclic_prefix_type;
} fapi_nr_subframe_config_t;
typedef struct {
uint16_t dl_carrier_bandwidth;
uint16_t ul_carrier_bandwidth;
uint16_t dl_absolutefrequencypointA;
uint16_t ul_absolutefrequencypointA;
uint16_t dl_offsettocarrier;
uint16_t ul_offsettocarrier;
uint16_t dl_subcarrierspacing;
uint16_t ul_subcarrierspacing;
uint16_t dl_specificcarrier_k0;
uint16_t ul_specificcarrier_k0;
uint16_t NIA_subcarrierspacing;
} fapi_nr_rf_config_t;
typedef struct {
uint16_t physical_cell_id;
uint8_t half_frame_index;
uint16_t ssb_subcarrier_offset;
uint16_t ssb_sib1_position_in_burst; // in sib1
uint64_t ssb_scg_position_in_burst; // in servingcellconfigcommon
uint8_t ssb_periodicity;
uint16_t ss_pbch_block_power;
uint16_t n_ssb_crb;
} fapi_nr_sch_config_t;
typedef struct {
uint16_t dl_bandwidth;
uint16_t ul_bandwidth;
uint16_t dl_offset;
uint16_t ul_offset;
uint8_t dl_subcarrierSpacing;
uint8_t ul_subcarrierSpacing;
} fapi_nr_initialBWP_config_t;
#define FAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS 16
#define FAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS 16
typedef struct {
uint16_t dmrs_TypeA_Position;
uint16_t num_PDSCHTimeDomainResourceAllocations;
uint16_t PDSCHTimeDomainResourceAllocation_k0[FAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
uint16_t PDSCHTimeDomainResourceAllocation_mappingType[FAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
uint16_t PDSCHTimeDomainResourceAllocation_startSymbolAndLength[FAPI_NR_PDSCH_CONFIG_MAXALLOCATIONS];
} fapi_nr_pdsch_config_t;
typedef struct {
uint16_t prach_RootSequenceIndex; ///// L1 parameter 'PRACHRootSequenceIndex'
uint16_t prach_msg1_SubcarrierSpacing; ///// L1 parameter 'prach-Msg1SubcarrierSpacing'
uint16_t restrictedSetConfig;
uint16_t msg3_transformPrecoding; ///// L1 parameter 'msg3-tp'
uint16_t ssb_perRACH_OccasionAndCB_PreamblesPerSSB;
uint16_t ra_ContentionResolutionTimer;
uint16_t rsrp_ThresholdSSB;
/////////////////--------------------NR RACH-ConfigGeneric--------------------/////////////////
uint16_t prach_ConfigurationIndex; ///// L1 parameter 'PRACHConfigurationIndex'
uint16_t prach_msg1_FDM; ///// L1 parameter 'prach-FDM'
uint16_t prach_msg1_FrequencyStart; ///// L1 parameter 'prach-frequency-start'
uint16_t zeroCorrelationZoneConfig;
uint16_t preambleReceivedTargetPower;
uint16_t preambleTransMax;
uint16_t powerRampingStep;
uint16_t ra_ResponseWindow;
} fapi_nr_rach_config_t;
typedef struct {
uint16_t groupHoppingEnabledTransformPrecoding; ///// L1 parameter 'Group-hopping-enabled-Transform-precoding'
uint16_t msg3_DeltaPreamble; ///// L1 parameter 'Delta-preamble-msg3'
uint16_t p0_NominalWithGrant; ///// L1 parameter 'p0-nominal-pusch-withgrant'
uint16_t dmrs_TypeA_Position;
uint16_t num_PUSCHTimeDomainResourceAllocations;
uint16_t PUSCHTimeDomainResourceAllocation_k2[FAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'K2'
uint16_t PUSCHTimeDomainResourceAllocation_mappingType[FAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS]; ///// L1 parameter 'Mapping-type'
uint16_t PUSCHTimeDomainResourceAllocation_startSymbolAndLength[FAPI_NR_PUSCH_CONFIG_MAXALLOCATIONS];
} fapi_nr_pusch_config_t;
typedef struct {
uint8_t pucch_resource_common;
uint16_t pucch_GroupHopping; ///// L1 parameter 'PUCCH-GroupHopping'
uint8_t hopping_id;
uint16_t p0_nominal; ///// L1 parameter 'p0-nominal-pucch'
} fapi_nr_pucch_config_t;
typedef struct {
uint8_t controlResourceSetZero;
uint8_t searchSpaceZero;
// fapi_nr_SearchSpace_t sib1searchSpace;
// fapi_nr_SearchSpace_t sibssearchSpace;
// fapi_nr_SearchSpace_t ra_SearchSpace;
} fapi_nr_pdcch_config_t;
typedef struct {
//NR TDD-UL-DL-ConfigCommon ///// L1 parameter 'UL-DL-configuration-common'
uint16_t referenceSubcarrierSpacing; ///// L1 parameter 'reference-SCS'
uint16_t dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity'
uint16_t nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots'
uint16_t nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common'
uint16_t nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots'
uint16_t nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common'
uint16_t Pattern2Present;
uint16_t Pattern2_dl_ul_periodicity; ///// L1 parameter 'DL-UL-transmission-periodicity'
uint16_t Pattern2_nrofDownlinkSlots; ///// L1 parameter 'number-of-DL-slots'
uint16_t Pattern2_nrofDownlinkSymbols; ///// L1 parameter 'number-of-DL-symbols-common'
uint16_t Pattern2_nrofUplinkSlots; ///// L1 parameter 'number-of-UL-slots'
uint16_t Pattern2_nrofUplinkSymbols; ///// L1 parameter 'number-of-UL-symbols-common'
} fapi_nr_tdd_ul_dl_config_t;
#define FAPI_MAX_NUM_RF_BANDS 16
typedef struct {
uint16_t number_rf_bands;
uint16_t rf_band[FAPI_MAX_NUM_RF_BANDS];
} fapi_rf_bands_t;
typedef struct
{
fapi_rf_bands_t rf_bands;
uint32_t nrarfcn;
// nfapi_nmm_frequency_bands_t nmm_gsm_frequency_bands;
// nfapi_nmm_frequency_bands_t nmm_umts_frequency_bands;
// nfapi_nmm_frequency_bands_t nmm_lte_frequency_bands;
// nfapi_uint8_tlv_t nmm_uplink_rssi_supported;
} fapi_nr_fapi_t;
typedef struct {
fapi_nr_fapi_t fapi_config;
fapi_nr_subframe_config_t subframe_config;
fapi_nr_rf_config_t rf_config;
fapi_nr_sch_config_t sch_config;
fapi_nr_initialBWP_config_t initialBWP_config;
fapi_nr_pdsch_config_t pdsch_config;
fapi_nr_rach_config_t rach_config;
fapi_nr_pusch_config_t pusch_config;
fapi_nr_pucch_config_t pucch_config;
fapi_nr_pdcch_config_t pdcch_config;
fapi_nr_tdd_ul_dl_config_t tdd_ul_dl_config;
// fapi_nr_ratematchpattern_t ratematchpattern;
// fapi_nr_ratematchpattern_lte_crs_t ratematchpattern_lte_crs;
} fapi_nr_config_request_t;
typedef struct {
fapi_nr_coreset_t coreset;
......@@ -544,19 +723,6 @@ typedef struct {
uint8_t p0_nominal;
} fapi_nr_pucch_config_common_t;
typedef struct {
uint8_t subcarrier_spacing_common;
uint8_t ssb_subcarrier_offset;
uint8_t dmrs_type_a_position;
uint8_t pdcch_config_sib1;
uint8_t cell_barred;
uint8_t intra_frequency_reselection;
uint16_t system_frame_number;
uint8_t ssb_index;
uint8_t half_frame_bit;
} fapi_nr_pbch_config_t;
typedef struct {
......@@ -693,7 +859,6 @@ typedef struct {
fapi_nr_pdsch_config_dedicated_t pdsch_config_dedicated;
fapi_nr_sps_config_t sps_config;
fapi_nr_radio_link_monitoring_config_t radio_link_monitoring_config;
} fapi_nr_dl_bwp_dedicated_config_t;
typedef struct {
......@@ -907,17 +1072,4 @@ typedef struct {
#define FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_DEDICATED 0x08
#define FAPI_NR_CONFIG_REQUEST_MASK_UL_BWP_DEDICATED 0x10
typedef struct {
uint32_t config_mask;
fapi_nr_pbch_config_t pbch_config; // MIB
fapi_nr_dl_bwp_common_config_t dl_bwp_common;
fapi_nr_dl_bwp_dedicated_config_t dl_bwp_dedicated;
fapi_nr_ul_bwp_common_config_t ul_bwp_common;
fapi_nr_ul_bwp_dedicated_config_t ul_bwp_dedicated;
} fapi_nr_config_request_t;
#endif
......@@ -44,11 +44,16 @@ typedef enum {
NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NBCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NPDCCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_NDLSCH_PDU_TYPE
} nfapi_nr_dl_config_pdu_type_e;
// nFAPI enums
typedef enum {
NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE = 0,
NFAPI_NR_UL_CONFIG_ULSCH_PDU_TYPE,
NFAPI_NR_UL_CONFIG_UCI_PDU_TYPE,
NFAPI_NR_UL_CONFIG_SRS_PDU_TYPE,
} nfapi_nr_ul_config_pdu_type_e;
//These TLVs are used exclusively by nFAPI
typedef struct
{
......@@ -251,6 +256,7 @@ typedef struct {
} nfapi_nr_pusch_config_t;
typedef struct {
uint8_t pucch_resource_common;
nfapi_uint16_tlv_t pucch_GroupHopping; ///// L1 parameter 'PUCCH-GroupHopping'
nfapi_uint16_tlv_t p0_nominal; ///// L1 parameter 'p0-nominal-pucch'
} nfapi_nr_pucch_config_t;
......@@ -655,18 +661,6 @@ typedef struct {
nfapi_nr_coreset_t pagingControlResourceSets;
}nfapi_nr_dl_config_pch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_nbch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_npdcch_pdu_rel15_t;
typedef struct {
} nfapi_nr_dl_config_ndlsch_pdu_rel15_t;
typedef struct {
nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15;
......@@ -682,11 +676,9 @@ typedef struct {
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
nfapi_nr_dl_config_nbch_pdu_rel15_t nbch_pdu_rel15;
nfapi_nr_dl_config_npdcch_pdu_rel15_t npdcch_pdu_rel15;
nfapi_nr_dl_config_ndlsch_pdu_rel15_t ndlsch_pdu_rel15;
};
} nfapi_nr_dl_config_request_pdu_t;
typedef struct {
nfapi_tl_t tl;
......@@ -739,9 +731,37 @@ typedef struct {
uint8_t beta_offset_ind;
} nfapi_nr_ul_config_ulsch_pdu_rel15_t;
typedef struct {
uint16_t rnti;
nfapi_nr_ul_config_ulsch_pdu_rel15_t ulsch_pdu_rel15;
} nfapi_nr_ul_config_ulsch_pdu;
typedef struct {
uint8_t pdu_type;
uint8_t pdu_size;
union {
// nfapi_nr_ul_config_uci_pdu uci_pdu;
nfapi_nr_ul_config_ulsch_pdu ulsch_pdu;
// nfapi_nr_ul_config_srs_pdu srs_pdu;
};
} nfapi_nr_ul_config_request_pdu_t;
typedef struct {
nfapi_tl_t tl;
uint8_t number_pdu;
nfapi_nr_ul_config_request_pdu_t *ul_config_pdu_list;
} nfapi_nr_ul_config_request_body_t;
typedef struct {
nfapi_p7_message_header_t header;
uint16_t sfn_sf;
nfapi_nr_ul_config_request_body_t ul_config_request_body;
nfapi_vendor_extension_tlv_t vendor_extension;
} nfapi_nr_ul_config_request_t;
#endif
......@@ -187,6 +187,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
cset_start_symb = pdcch_params.first_symbol;
cset_nsymb = pdcch_params.n_symb;
dci_idx = 0;
LOG_D(PHY, "Coreset rb_offset %d\n",pdcch_params.rb_offset);
LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
// DMRS length is per OFDM symbol
uint16_t dmrs_length = (pdcch_params.precoder_granularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS)?
......
......@@ -184,7 +184,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
pos=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
LOG_D(PHY,"frequency-domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu);
LOG_D(PHY,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_alloc->size-pos,*dci_pdu);
#endif
// Time domain assignment
pos+=4;
......@@ -219,7 +219,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
pos++;
*dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
LOG_D(PHY,"Format indicator %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->format_indicator,1,dci_alloc->size-pos,*dci_pdu);
LOG_D(PHY,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",pdu_rel15->format_indicator,1,N_RB,dci_alloc->size-pos,*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16)
......
......@@ -645,3 +645,4 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
if (gNB) stop_meas(&gNB->rx_prach);
}
......@@ -778,7 +778,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
// For each BWP the number of CORESETs is limited to 3 (including initial CORESET Id=0 -> ControlResourceSetId (0..maxNrofControlReourceSets-1) (0..12-1)
//uint32_t n_BWP_start = 0;
//uint32_t n_rb_offset = 0;
uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset/*+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)*/;
uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset;/*+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB);*/
// start time position for CORESET
// parameter symbol_mon is a 14 bits bitmap indicating monitoring symbols within a slot
uint8_t start_symbol = 0;
......
......@@ -89,6 +89,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
uint8_t CC_id = Sched_INFO->CC_id;
nfapi_nr_dl_config_request_t *DL_req = Sched_INFO->DL_req;
nfapi_tx_request_t *TX_req = Sched_INFO->TX_req;
nfapi_nr_ul_config_request_t *UL_req = Sched_INFO->UL_req;
frame_t frame = Sched_INFO->frame;
sub_frame_t slot = Sched_INFO->slot;
......@@ -98,10 +99,9 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
gNB = RC.gNB[Mod_id];
uint8_t number_dl_pdu = DL_req->dl_config_request_body.number_pdu;
uint8_t number_ul_pdu = UL_req->ul_config_request_body.number_pdu;
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu;
int i;
LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SF:%04d%d DL_req:SFN/SF:%04d%d:dl_pdu:%d tx_req:SFN/SF:%04d%d:pdus:%d \n",
frame,slot,
......@@ -115,8 +115,8 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
gNB->pdcch_vars.num_dci=0;
for (i=0;i<number_dl_pdu;i++) {
dl_config_pdu = &DL_req->dl_config_request_body.dl_config_pdu_list[i];
for (int i=0;i<number_dl_pdu;i++) {
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu = &DL_req->dl_config_request_body.dl_config_pdu_list[i];
LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type);
switch (dl_config_pdu->pdu_type) {
case NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE:
......@@ -162,4 +162,13 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
oai_nfapi_nr_dl_config_req(Sched_INFO->DL_req); // DJP - .dl_config_request_body.dl_config_pdu_list[0]); // DJP - FIXME TODO - yuk - only copes with 1 pdu
}
for (int i=0;i<number_ul_pdu;i++) {
nfapi_nr_ul_config_request_pdu_t *ul_config_pdu = &UL_req->ul_config_request_body.ul_config_pdu_list[i];
LOG_D(PHY,"NFAPI: ul_pdu %d : type %d\n",i,ul_config_pdu->pdu_type);
switch (ul_config_pdu->pdu_type) {
case NFAPI_NR_UL_CONFIG_ULSCH_PDU_TYPE:
//handle_nr_nfapi_ulsch_pdu(gNB,frame,slot,&ul_config_pdu->ulsch_pdu);
break;
}
}
}
......@@ -123,7 +123,9 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t e
@param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
@param phy_vars_rn pointer to RN variables
*/
int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t do_pdcch_flag,runmode_t mode,fapi_nr_pbch_config_t pbch_config);
int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,
uint8_t do_pdcch_flag,runmode_t mode,
fapi_nr_dl_config_request_t *DLconfigreq);
int phy_procedures_slot_parallelization_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode,relaying_type_t r_type);
......
......@@ -136,54 +136,54 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
if(scheduled_response->ul_config != NULL){
fapi_nr_ul_config_request_t *ul_config = scheduled_response->ul_config;
for(i=0; i<ul_config->number_pdus; ++i){
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH){
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_ULSCH){
// pusch config pdu
fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15;
uint8_t current_harq_pid = pusch_config_pdu->harq_process_nbr;
ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs;
ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb;
ulsch0->harq_processes[current_harq_pid]->nb_symbols = pusch_config_pdu->number_symbols;
ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol;
ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs;
ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi;
ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv;
ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
fapi_nr_ul_config_ulsch_pdu_rel15_t *ulsch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15;
uint8_t current_harq_pid = ulsch_config_pdu->harq_process_nbr;
ulsch0->harq_processes[current_harq_pid]->nb_rb = ulsch_config_pdu->number_rbs;
ulsch0->harq_processes[current_harq_pid]->first_rb = ulsch_config_pdu->start_rb;
ulsch0->harq_processes[current_harq_pid]->nb_symbols = ulsch_config_pdu->number_symbols;
ulsch0->harq_processes[current_harq_pid]->start_symbol = ulsch_config_pdu->start_symbol;
ulsch0->harq_processes[current_harq_pid]->mcs = ulsch_config_pdu->mcs;
ulsch0->harq_processes[current_harq_pid]->DCINdi = ulsch_config_pdu->ndi;
ulsch0->harq_processes[current_harq_pid]->rvidx = ulsch_config_pdu->rv;
ulsch0->f_pusch = ulsch_config_pdu->absolute_delta_PUSCH;
}
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_UCI){
// pucch config pdu
fapi_nr_ul_config_pucch_pdu *pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu;
fapi_nr_ul_config_uci_pdu *uci_config_pdu = &ul_config->ul_config_list[i].uci_config_pdu;
uint8_t pucch_resource_id = 0; //FIXME!!!
uint8_t format = 1; // FIXME!!!
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index;
PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = puc