- Sep 30, 2016
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laurent authored
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- Sep 10, 2016
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knopp authored
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- Sep 08, 2016
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wluhan authored
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- Sep 03, 2016
- Aug 25, 2016
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Rohit Gupta authored
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knopp authored
changes for oaisim to function with new threading architecture and trx_read/trx_write emulation. Tested for 5/10 MHz TM1. Multiple-antenna mode fails.
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- Aug 07, 2016
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Raymond Knopp authored
usrp 20 MHz on 30.72 master clock. fixed memory leak in prach.c for 20 MHz with 3/4 sampling. added default attributes to threads in lte-enb.c
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Raymond Knopp authored
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knopp authored
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knopp authored
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knopp authored
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- Aug 06, 2016
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Raymond Knopp authored
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knopp authored
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- Aug 05, 2016
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Raymond Knopp authored
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knopp authored
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knopp authored
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- Aug 04, 2016
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knopp authored
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- Aug 03, 2016
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Raymond Knopp authored
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knopp authored
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- Aug 01, 2016
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Raymond Knopp authored
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knopp authored
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- Jul 31, 2016
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Raymond Knopp authored
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knopp authored
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Raymond Knopp authored
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Raymond Knopp authored
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- Jul 29, 2016
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Cédric Roux authored
5ms by default, easy to change (change the 10 in the loops) if the behavior is worse than before, do git revert [commit ID]
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- Jul 28, 2016
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Cédric Roux authored
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Cédric Roux authored
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- Jul 27, 2016
- Jul 26, 2016
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Sandeep Kumar authored
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knopp authored
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- Jul 25, 2016
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Sandeep Kumar authored
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- Jul 24, 2016
- Jul 23, 2016
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knopp authored
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- Jul 22, 2016
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Sandeep Kumar authored
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Sandeep Kumar authored
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