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timer
4b2187a7
·
Fixed timer issue
·
May 31, 2017
fixlatches
c8154a2e
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New output of synthesis
·
Jun 01, 2017
debug
3c112224
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Synthesis logs and boot.bin
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Jun 01, 2017
resetbtn-debug
74ec06aa
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New debouncer on our rst button with strict margins
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Jun 03, 2017
strictmargins
a3dffbbd
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Move master to strictmargins branch
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Jun 03, 2017
axi_version_new
4bb0ddac
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update to most recent ctrl sim
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Jun 07, 2017
documentation
495243ea
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Update README.md
·
Jun 08, 2017
trysample
7be2d16b
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revert to previous commit before register for araddr
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Jun 08, 2017
oldworking
4cbb733f
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New version of old working bin
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Jun 08, 2017
NewCS
c5b53e77
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New checksum
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Jun 08, 2017
debugChecksumSA
5b5986c7
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Just kidding, last bins were wrong. These are really new asynch CS and SA local bins.
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Jun 08, 2017
checksumToDatamuxTo8mux
6492b6f6
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Reordering things
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Jun 09, 2017
axi_debug
c8cfe7ce
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Again make CS synchronous
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Jun 09, 2017
debugchecksumSync
1aa5ebc6
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Synchronous boot.bin: hopefully work?
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Jun 09, 2017
asyncNewChecksumNick
3d7fcde2
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new compiler errors
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Jun 09, 2017
asyncNewChecksum
dc49b5d6
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Merge with sa_sim. Compilable.
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Jun 09, 2017
prof-checksum
34c7b640
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Boot.bin with no synthesis warnings
·
Jun 12, 2017
new_axi
b0dbdbf7
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Removed redundant part in log
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Jun 12, 2017
master
default
protected
7ca27ebb
·
Updated AXI result in README
·
Jun 12, 2017