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Commit 6f6f9acb authored by Thomas Laurent's avatar Thomas Laurent
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merge develop; add option to set affinity in UE

parents 23c75476 b2b1dc9f
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cmake_targets/CMakeLists.txt
View file @ 6f6f9acb
......@@ -1871,6 +1871,7 @@ add_executable(oaisim
${OPENAIR_TARGETS}/SIMU/USER/oaisim_functions.c
${OPENAIR_TARGETS}/SIMU/USER/event_handler.c
${OPENAIR_TARGETS}/SIMU/USER/oaisim.c
${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
${OPENAIR2_DIR}/RRC/NAS/nas_config.c
${OPENAIR2_DIR}/RRC/NAS/rb_config.c
${OPENAIR3_DIR}/NAS/UE/nas_ue_task.c
......@@ -1885,7 +1886,7 @@ add_executable(oaisim
target_include_directories(oaisim PUBLIC ${OPENAIR_TARGETS}/SIMU/USER)
target_link_libraries (oaisim
-Wl,--start-group
-Wl,-ldl,--start-group
RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB GTPV1U SECU_CN UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB PHY LFDS ${MSC_LIB} L2 ${RAL_LIB} LIB_NAS_UE SIMU SIMU_ETH SECU_OSA ${ITTI_LIB} ${MIH_LIB}
-Wl,--end-group )
......@@ -1916,6 +1917,7 @@ add_executable(oaisim_nos1
${OPENAIR_TARGETS}/SIMU/USER/oaisim_functions.c
${OPENAIR_TARGETS}/SIMU/USER/event_handler.c
${OPENAIR_TARGETS}/SIMU/USER/oaisim.c
${OPENAIR_TARGETS}/ARCH/COMMON/common_lib.c
${OPENAIR2_DIR}/RRC/NAS/nas_config.c
${OPENAIR2_DIR}/RRC/NAS/rb_config.c
${OPENAIR_TARGETS}/COMMON/create_tasks.c
......
cmake_targets/autotests/v2/actions/execution_compile.bash
View file @ 6f6f9acb
......@@ -3,6 +3,9 @@ source oaienv
cd cmake_targets
rm -rf log
mkdir -p log
echo $PRE_BUILD
bash -c "$PRE_BUILD"
echo $BUILD_PROG $BUILD_ARGUMENTS
$BUILD_PROG $BUILD_ARGUMENTS
echo $PRE_EXEC
bash -c "$PRE_EXEC"
cmake_targets/build_oai
View file @ 6f6f9acb
......@@ -418,9 +418,9 @@ function main() {
if [ "$oaisim" = "1" ] ; then
#to be discussed
# there is no RF device and no transport protocol
# there is no RF device transport protocol
HW="None"
TP="None"
TP="ETHERNET"
if [ "$XFORMS" == "True" ] ; then
PRINT_STATS="True"
......@@ -671,6 +671,15 @@ function main() {
# CMakeFiles/oai_nw_drv/oai_nw_drv.ko $dbin/oai_nw_drv.ko
fi
if [ "$TP" == "ETHERNET" ] ; then
compilations \
$oaisim_build_dir oai_eth_transpro \
liboai_eth_transpro.so $dbin/liboai_eth_transpro.so.$REL
ln -s liboai_eth_transpro.so liboai_transpro.so
ln -s $dbin/liboai_eth_transpro.so.$REL $dbin/liboai_transpro.so
echo_info "liboai_transpro.so is linked with ETHERNET library"
fi
cmake_file=$DIR/oaisim_mme_build_oai/CMakeLists.txt
cp $DIR/oaisim_mme_build_oai/CMakeLists.template $cmake_file
echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
......
cmake_targets/tools/build_helper
View file @ 6f6f9acb
......@@ -171,7 +171,7 @@ install_protobuf_from_source(){
echo "Downloading protobuf"
rm -rf /tmp/protobuf-2.6.1.tar.gz* /tmp/protobuf-2.6.1
wget https://github.com/google/protobuf/releases/download/v2.6.1/protobuf-2.6.1.tar.gz
tar -xzvf protobuf-2.6.1.tar.gz
tar -xzvf protobuf-2.6.1.tar.gz --owner $USER --group $USER --no-same-owner
cd protobuf-2.6.1/
./configure
echo "Compiling protobuf"
......@@ -208,8 +208,8 @@ check_install_usrp_uhd_driver(){
#The new USRP repository
$SUDO add-apt-repository ppa:ettusresearch/uhd -y
$SUDO apt-get update
$SUDO apt-get -y install python python-tk libboost-all-dev libusb-1.0-0-dev
$SUDO apt-get -y install libuhd-dev libuhd003 uhd-host
$SUDO apt-get -y --allow-unauthenticated install python python-tk libboost-all-dev libusb-1.0-0-dev
$SUDO apt-get -y --allow-unauthenticated install libuhd-dev libuhd003 uhd-host
}
install_usrp_uhd_driver() {
......@@ -224,9 +224,9 @@ check_install_bladerf_driver(){
$SUDO add-apt-repository -y ppa:bladerf/bladerf
$SUDO apt-get update
fi
$SUDO apt-get install -y bladerf libbladerf-dev
$SUDO apt-get install -y bladerf-firmware-fx3
$SUDO apt-get install -y bladerf-fpga-hostedx40
$SUDO apt-get install -y--allow-unauthenticated bladerf libbladerf-dev
$SUDO apt-get install -y --allow-unauthenticated bladerf-firmware-fx3
$SUDO apt-get install -y --allow-unauthenticated bladerf-fpga-hostedx40
}
flash_firmware_bladerf() {
......
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @ 6f6f9acb
......@@ -3831,6 +3831,8 @@ int generate_ue_dlsch_params_from_dci(int frame,
LTE_UE_DLSCH_t *dlsch0=NULL,*dlsch1=NULL;
LTE_DL_UE_HARQ_t *dlsch0_harq,*dlsch1_harq;
if (!dlsch[0]) return -1;
#ifdef DEBUG_DCI
LOG_D(PHY,"dci_tools.c: Filling ue dlsch params -> rnti %x, SFN/SF %d/%d, dci_format %s\n",
rnti,
......@@ -7395,8 +7397,8 @@ int generate_eNB_ulsch_params_from_dci(PHY_VARS_eNB *eNB,
rb_alloc = rballoc;
if (rb_alloc>RIV_max) {
LOG_E(PHY,"Format 0: rb_alloc > RIV_max\n");
mac_xface->macphy_exit("Format 0: rb_alloc > RIV_max\n");
LOG_E(PHY,"Format 0: rb_alloc (%d) > RIV_max (%d)\n",rb_alloc,RIV_max);
mac_xface->macphy_exit("Format 0: error");
return(-1);
}
......
openair1/PHY/LTE_TRANSPORT/if4_tools.c
View file @ 6f6f9acb
......@@ -108,8 +108,8 @@ void send_IF4p5(PHY_VARS_eNB *eNB, int frame, int subframe, uint16_t packet_type
(packet_type == IF4p5_PULTICK)){
db_fulllength = 12*fp->N_RB_UL;
db_halflength = (db_fulllength)>>1;
slotoffsetF = 1;
blockoffsetF = slotoffsetF + fp->ofdm_symbol_size - db_halflength - 1;
slotoffsetF = 0;
blockoffsetF = slotoffsetF + fp->ofdm_symbol_size - db_halflength;
if (subframe_select(fp,subframe)==SF_S) {
nsym=fp->ul_symbols_in_S_subframe;
......@@ -131,10 +131,12 @@ void send_IF4p5(PHY_VARS_eNB *eNB, int frame, int subframe, uint16_t packet_type
LOG_D(PHY,"IF4p5_PULFFT: frame %d, subframe %d, symbol %d\n",frame,subframe,symbol_id);
for (element_id=0; element_id<db_halflength; element_id++) {
i = (uint16_t*) &rxdataF[0][blockoffsetF+element_id];
data_block[element_id] = ((uint16_t) lin2alaw[*i]) | (lin2alaw[*(i+1)]<<8);
data_block[element_id] = ((uint16_t) lin2alaw[*i]) | ((uint16_t)(lin2alaw[*(i+1)]<<8));
i = (uint16_t*) &rxdataF[0][slotoffsetF+element_id];
data_block[element_id+db_halflength] = ((uint16_t) lin2alaw[*i]) | (lin2alaw[*(i+1)]<<8);
data_block[element_id+db_halflength] = ((uint16_t) lin2alaw[*i]) | ((uint16_t)(lin2alaw[*(i+1)]<<8));
//if (element_id==0) LOG_I(PHY,"send_if4p5: symbol %d rxdata0 = (%d,%d)\n",symbol_id,*i,*(i+1));
}
packet_header->frame_status &= ~(0x000f<<26);
......@@ -235,7 +237,7 @@ void recv_IF4p5(PHY_VARS_eNB *eNB, int *frame, int *subframe, uint16_t *packet_t
0) < 0) {
perror("ETHERNET read");
}
if (eth->flags == ETH_RAW_IF4p5_MODE) {
packet_header = (IF4p5_header_t*) (rx_buffer+MAC_HEADER_SIZE_BYTES);
data_block = (uint16_t*) (rx_buffer+MAC_HEADER_SIZE_BYTES+sizeof_IF4p5_header_t);
......@@ -251,7 +253,6 @@ void recv_IF4p5(PHY_VARS_eNB *eNB, int *frame, int *subframe, uint16_t *packet_t
*packet_type = packet_header->sub_type;
if (*packet_type == IF4p5_PDLFFT) {
*symbol_number = ((packet_header->frame_status)>>26)&0x000f;
......@@ -273,10 +274,10 @@ void recv_IF4p5(PHY_VARS_eNB *eNB, int *frame, int *subframe, uint16_t *packet_t
} else if (*packet_type == IF4p5_PULFFT) {
*symbol_number = ((packet_header->frame_status)>>26)&0x000f;
if (eNB->CC_id==1) LOG_I(PHY,"UL_IF4p5: CC_id %d : frame %d, subframe %d, symbol %d\n",eNB->CC_id,*frame,*subframe,*symbol_number);
if (eNB->CC_id==0) LOG_D(PHY,"UL_IF4p5: CC_id %d : frame %d, subframe %d, symbol %d\n",eNB->CC_id,*frame,*subframe,*symbol_number);
slotoffsetF = (*symbol_number)*(fp->ofdm_symbol_size) + 1;
blockoffsetF = slotoffsetF + fp->ofdm_symbol_size - db_halflength - 1;
slotoffsetF = (*symbol_number)*(fp->ofdm_symbol_size);
blockoffsetF = slotoffsetF + fp->ofdm_symbol_size - db_halflength;
for (element_id=0; element_id<db_halflength; element_id++) {
i = (uint16_t*) &rxdataF[0][blockoffsetF+element_id];
......@@ -286,9 +287,12 @@ void recv_IF4p5(PHY_VARS_eNB *eNB, int *frame, int *subframe, uint16_t *packet_t
i = (uint16_t*) &rxdataF[0][slotoffsetF+element_id];
*i = alaw2lin[ (data_block[element_id+db_halflength] & 0xff) ];
*(i+1) = alaw2lin[ (data_block[element_id+db_halflength]>>8) ];
//if (element_id==0) LOG_I(PHY,"recv_if4p5: symbol %d rxdata0 = (%u,%u)\n",*symbol_number,*i,*(i+1));
}
} else if (*packet_type == IF4p5_PRACH) {
} else if (*packet_type == IF4p5_PRACH) {
LOG_D(PHY,"PRACH_IF4p5: CC_id %d : frame %d, subframe %d, symbol %d\n",eNB->CC_id,*frame,*subframe);
if (eNB->CC_id==1) LOG_I(PHY,"PRACH_IF4p5: CC_id %d : frame %d, subframe %d, symbol %d\n",eNB->CC_id,*frame,*subframe);
// FIX: hard coded prach samples length
......
openair1/PHY/LTE_TRANSPORT/prach.c
View file @ 6f6f9acb
......@@ -645,6 +645,12 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
#else //normal case (simulation)
prach_start = subframe*ue->frame_parms.samples_per_tti-ue->N_TA_offset;
LOG_D(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id,
prach_start,
ue->rx_offset,
ue->hw_timing_advance,
ue->N_TA_offset);
#endif
......@@ -1074,6 +1080,8 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
#ifdef PRACH_DEBUG
write_output("prach_txF0.m","prachtxF0",prachF,prach_len-Ncp,1,1);
write_output("prach_tx0.m","prachtx0",prach+(Ncp<<1),prach_len-Ncp,1,1);
write_output("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][0]),2*ue->frame_parms.samples_per_tti,1,1);
exit(-1);
#endif
return signal_energy( (int*)prach, 256 );
......@@ -1125,7 +1133,7 @@ void rx_prach(PHY_VARS_eNB *eNB,
int fft_size,log2_ifft_size;
uint8_t nb_ant_rx = 1; //eNB->frame_parms.nb_antennas_rx;
// int en;
int en;
for (aa=0; aa<nb_ant_rx; aa++) {
prach[aa] = (int16_t*)&eNB->common_vars.rxdata[0][aa][subframe*eNB->frame_parms.samples_per_tti-eNB->N_TA_offset];
......@@ -1327,9 +1335,26 @@ void rx_prach(PHY_VARS_eNB *eNB,
/// **** send_IF4 of rxsigF to RCC **** ///
send_IF4p5(eNB, eNB->proc.frame_prach, eNB->proc.subframe_prach, IF4p5_PRACH, k);
// en = dB_fixed(signal_energy(&rxsigF[0][k],840));
// if (en>60)
// printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);
#if 0
/* TODO: resolv this conflict (there should be no printf anyway, so no big deal) */
<<<<<<< HEAD
/*
en = dB_fixed(signal_energy(&rxsigF[0][k],840));
printf("Sending PRACH, k %d,n_ra_prb %d, N_RB_UL %d, en %d\n",k,n_ra_prb,eNB->frame_parms.N_RB_UL,en);
if (en>60) {
printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);
write_output("prach_rx0.m","prach_rx0",(int16_t*)&rxsigF[0][k],839,1,1);
exit(-1);
}
*/
=======
en = dB_fixed(signal_energy(&rxsigF[0][k],840));
if (en>60)
printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);
>>>>>>> origin/fix-if4p5
#endif
return;
} else if (eNB->node_function == NGFI_RCC_IF4p5) {
k = (12*n_ra_prb) - 6*eNB->frame_parms.N_RB_UL;
......@@ -1347,9 +1372,25 @@ void rx_prach(PHY_VARS_eNB *eNB,
(&rxsigF[0][0]),
839*2*sizeof(int16_t));
//en = dB_fixed(signal_energy(&rxsigF[0][k],840));
// if (en>60)
//printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);
#if 0
/* TODO: resolv this conflict (there should be no printf anyway, so no big deal) */
<<<<<<< HEAD
/*
en = dB_fixed(signal_energy(&rxsigF[0][k],840));
printf("Receiving PRACH, k %d,n_ra_prb %d, N_RB_UL %d, en %d\n",k,n_ra_prb,eNB->frame_parms.N_RB_UL,en);
if (en>60) {
printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);
write_output("prach_rx0.m","prach_rx0",(int16_t*)&rxsigF[0][k],839,1,1);
exit(-1);
}
*/
=======
en = dB_fixed(signal_energy(&rxsigF[0][k],840));
/*if (en>60)
printf("PRACH: Frame %d, Subframe %d => %d dB\n",eNB->proc.frame_rx,eNB->proc.subframe_rx,en);*/
>>>>>>> origin/fix-if4p5
#endif
}
......@@ -1523,7 +1564,7 @@ void rx_prach(PHY_VARS_eNB *eNB,
#ifdef PRACH_DEBUG
// if (en>40) {
if (en>40) {
k = (12*n_ra_prb) - 6*eNB->frame_parms.N_RB_UL;
if (k<0)
......@@ -1537,7 +1578,7 @@ void rx_prach(PHY_VARS_eNB *eNB,
write_output("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1);
write_output("prach_ifft0.m","prach_t0",prach_ifft[0],1024,1,1);
exit(-1);
// }
}
#endif
} // new dft
......@@ -1551,7 +1592,7 @@ void rx_prach(PHY_VARS_eNB *eNB,
for (aa=0; aa<nb_ant_rx; aa++) {
lev += (int32_t)prach_ifft[aa][(preamble_shift2+i)<<1]*prach_ifft[aa][(preamble_shift2+i)<<1] + (int32_t)prach_ifft[aa][1+((preamble_shift2+i)<<1)]*prach_ifft[aa][1+((preamble_shift2+i)<<1)];
}
levdB = dB_fixed_times10(lev);
if (levdB>preamble_energy_list[preamble_index] ) {
......@@ -1559,12 +1600,12 @@ void rx_prach(PHY_VARS_eNB *eNB,
preamble_delay_list[preamble_index] = (i*fft_size)>>log2_ifft_size;
}
}
#ifdef PRACH_DEBUG
LOG_D(PHY,"[RAPROC] Preamble %d => %d dB, %d (shift %d (%d), NCS2 %d(%d), Ncp %d)\n",preamble_index,preamble_energy_list[preamble_index],preamble_delay_list[preamble_index],preamble_shift2,
preamble_shift, NCS2,NCS,Ncp);
#endif
// exit(-1);
#endif
}// preamble_index
stop_meas(&eNB->rx_prach);
......
openair1/PHY/LTE_TRANSPORT/ulsch_modulation.c
View file @ 6f6f9acb
......@@ -415,7 +415,7 @@ void ulsch_modulation(int32_t **txdataF,
return;
}
if (first_rb >25 ) {
if (first_rb > frame_parms->N_RB_UL) {
printf("ulsch_modulation.c: Frame %d, Subframe %d Illegal first_rb %d\n",frame,subframe,first_rb);
return;
}
......
openair1/PHY/defs.h
View file @ 6f6f9acb
......@@ -434,6 +434,7 @@ typedef struct PHY_VARS_eNB_s {
eNB_proc_t proc;
eNB_func_t node_function;
eNB_timing_t node_timing;
eth_params_t *eth_params;
int single_thread_flag;
openair0_rf_map rf_map;
int abstraction_flag;
......
openair1/SCHED/phy_mac_stub.c
View file @ 6f6f9acb
......@@ -455,6 +455,151 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
break;
}
DCI_pdu->dci_alloc[1].L = 2;
DCI_pdu->dci_alloc[1].rnti = 0x1235;
DCI_pdu->dci_alloc[1].format = format0;
DCI_pdu->dci_alloc[1].ra_flag = 0;
if (eNB->frame_parms.frame_type == FDD) {
switch (eNB->frame_parms.N_RB_DL) {
case 6:
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(6,1,4);
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_1_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
/* case 15:
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_3MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case 25:
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,1,20);
printf("rballoc %d\n",((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc);
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_5MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
case 50:
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(50,1,48);
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_10MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
/* case 75:
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_15MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case 100:
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(100,1,96);
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_20MHz_FDD_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
}
}
else {
switch (eNB->frame_parms.N_RB_DL==6) {
case 6:
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(6,1,5);
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_1_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
/* case 15:
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_3MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case 25:
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,20);
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_5MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
case 50:
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(50,1,48);
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_10MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
/* case 75:
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_15MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;*/
case 100:
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->type = 0;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->hopping = 0;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->rballoc = computeRIV(100,1,96);
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->mcs = eNB->target_ue_ul_mcs;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->ndi = proc->frame_tx&1;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->TPC = 0;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cshift = 0;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->dai = 0;
((DCI0_20MHz_TDD_1_6_t*)&DCI_pdu->dci_alloc[1].dci_pdu[0])->cqi_req = 1;
break;
}
}
} else if (transmission_mode==4) {
DCI_pdu->Num_ue_spec_dci = 1;
// user 1
......@@ -543,32 +688,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],&RA_alloc_pdu,sizeof(DCI1A_5MHz_TDD_1_6_t));
break;
*/
/*
case 9:
DCI_pdu->Num_ue_spec_dci = 1;
//user 1
if (eNB->frame_parms.frame_type == FDD)
DCI_pdu->dci_alloc[0].dci_length = sizeof_DCI0_5MHz_FDD_t ;
else
DCI_pdu->dci_alloc[0].dci_length = sizeof_DCI0_5MHz_TDD_1_6_t ;
DCI_pdu->dci_alloc[0].L = 2;
DCI_pdu->dci_alloc[0].rnti = 0x1235;
DCI_pdu->dci_alloc[0].format = format0;
DCI_pdu->dci_alloc[0].ra_flag = 0;
UL_alloc_pdu.type = 0;
UL_alloc_pdu.hopping = 0;
UL_alloc_pdu.rballoc = computeRIV(25,2,eNB->ue_ul_nb_rb);
UL_alloc_pdu.mcs = eNB->target_ue_ul_mcs;
UL_alloc_pdu.ndi = proc->frame_tx&1;
UL_alloc_pdu.TPC = 0;
UL_alloc_pdu.cshift = 0;
UL_alloc_pdu.dai = 0;
UL_alloc_pdu.cqi_req = 1;
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t));
*/
// user 2
/*
DCI_pdu->dci_alloc[1].dci_length = sizeof_DCI0_5MHz_TDD_1_6_t ;
......@@ -593,11 +714,8 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
UL_alloc_pdu.dai = 0;
UL_alloc_pdu.cqi_req = 1;
memcpy((void*)&DCI_pdu->dci_alloc[1].dci_pdu[0],(void *)&UL_alloc_pdu,sizeof(DCI0_5MHz_TDD_1_6_t));
break;
*/
/*default:
break;*/
}
/*
......
openair1/SCHED/phy_procedures_lte_eNb.c
View file @ 6f6f9acb
......@@ -92,6 +92,9 @@ extern uint16_t hundred_times_log10_NPRB[100];
unsigned int max_peak_val;
int max_sync_pos;
int harq_pid_updated[NUMBER_OF_UE_MAX][8] = {{0}};
int harq_pid_round[NUMBER_OF_UE_MAX][8] = {{0}};
//DCI_ALLOC_t dci_alloc[8];
#ifdef EMOS
......@@ -1444,15 +1447,6 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
eNB->dlsch_ra->active = 0;
}
#if defined(FLEXRAN_AGENT_SB_IF)
#ifndef DISABLE_SF_TRIGGER
//Send subframe trigger to the controller
if (mac_agent_registered[eNB->Mod_id]) {
agent_mac_xface[eNB->Mod_id]->flexran_agent_send_sf_trigger(eNB->Mod_id);
}
#endif
#endif
// Now scan UE specific DLSCH
for (UE_id=0; UE_id<NUMBER_OF_UE_MAX; UE_id++)
{
......@@ -1553,7 +1547,6 @@ void process_HARQ_feedback(uint8_t UE_id,
int subframe = proc->subframe_rx;
int harq_pid = subframe2harq_pid( fp,frame,subframe);
if (fp->frame_type == FDD) { //FDD
subframe_m4 = (subframe<4) ? subframe+6 : subframe-4;
......@@ -1681,6 +1674,7 @@ void process_HARQ_feedback(uint8_t UE_id,
mp = m;
dl_harq_pid[m] = dlsch->harq_ids[dl_subframe];
harq_pid_updated[UE_id][dl_harq_pid[m]] = 1;
if ((pucch_sel != 2)&&(pusch_flag == 0)) { // multiplexing
if ((SR_payload == 1)&&(all_ACKed == 1))
......@@ -1768,7 +1762,7 @@ void process_HARQ_feedback(uint8_t UE_id,
eNB->dlsch[(uint8_t)UE_id][0]->harq_processes[dl_harq_pid[m]]->TBS;
*/
}
// Do fine-grain rate-adaptation for DLSCH
if (ue_stats->dlsch_NAK_round0 > dlsch->error_threshold) {
if (ue_stats->dlsch_mcs_offset == 1)
......@@ -1781,7 +1775,7 @@ void process_HARQ_feedback(uint8_t UE_id,
LOG_D(PHY,"[process_HARQ_feedback] Frame %d Setting round to %d for pid %d (subframe %d)\n",frame,
dlsch_harq_proc->round,dl_harq_pid[m],subframe);
#endif
harq_pid_round[UE_id][dl_harq_pid[m]] = dlsch_harq_proc->round;
// Clear NAK stats and adjust mcs offset
// after measurement window timer expires
if (ue_stats->dlsch_sliding_cnt == dlsch->ra_window_size) {
......@@ -1800,8 +1794,6 @@ void process_HARQ_feedback(uint8_t UE_id,
ue_stats->dlsch_NAK_round0 = 0;
ue_stats->dlsch_sliding_cnt = 0;
}
}