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oai
openairinterface5G
Commits
be5f62a9
Commit
be5f62a9
authored
Feb 21, 2019
by
Florian Kaltenberger
Browse files
Merge branch 'nr_pdcch_updates' into 'develop-nr'
Nr pdcch updates See merge request
!514
parents
5bb6985f
8c983da4
Changes
27
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Side-by-side
cmake_targets/CMakeLists.txt
View file @
be5f62a9
...
...
@@ -2651,7 +2651,7 @@ if (${T_TRACER})
#all "add_executable" definitions (except tests, rb_tool, updatefw)
lte-softmodem lte-softmodem-nos1 lte-uesoftmodem lte-uesoftmodem-nos1
nr-softmodem nr-softmodem-nos1 nr-uesoftmodem nr-uesoftmodem-nos1
dlsim_tm4 dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
dlsim_tm4
nr_
dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
pdcchsim pucchsim prachsim syncsim ulsim
ldpctest polartest
#all "add_library" definitions
...
...
maketags
View file @
be5f62a9
#!/bin/sh
echo
"building ctags for openair1 and openair2 ..."
ctags
-e
-R
--exclude
=
openair1/DOCS/
--exclude
=
openair2/DOCS/
--exclude
=
openair
2/RRC/CELLULAR/
--exclude
=
openair2/NAS/DRIVER/CELLULAR/
--exclude
=
openair2
/SIMULATION/
--exclude
=
targets/DOCS/
--exclude
=
targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi
ctags
-e
-R
--exclude
=
openair1/DOCS/
--exclude
=
openair2/DOCS/
--exclude
=
openair
1
/SIMULATION/
--exclude
=
targets/DOCS/
--exclude
=
targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
View file @
be5f62a9
...
...
@@ -13,6 +13,9 @@
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
#define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64
#define NFAPI_NR_MAX_NB_CORESETS 12
#define NFAPI_NR_MAX_NB_SEARCH_SPACES 40
// Extension to the generic structures for single tlv values
typedef
struct
{
...
...
@@ -356,7 +359,8 @@ typedef enum {
typedef
enum
{
NFAPI_NR_CSET_CONFIG_MIB_SIB1
=
0
,
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
,
// implicit assumption of coreset Id other than 0
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG_CSET_0
}
nfapi_nr_coreset_config_type_e
;
typedef
enum
{
...
...
@@ -364,6 +368,31 @@ typedef enum {
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
}
nfapi_nr_coreset_precoder_granularity_type_e
;
typedef
enum
{
NFAPI_NR_QCL_TYPE_A
=
0
,
NFAPI_NR_QCL_TYPE_B
,
NFAPI_NR_QCL_TYPE_C
,
NFAPI_NR_QCL_TYPE_D
}
nfapi_nr_qcl_type_e
;
typedef
enum
{
NFAPI_NR_SS_PERIODICITY_SL1
=
1
,
NFAPI_NR_SS_PERIODICITY_SL2
=
2
,
NFAPI_NR_SS_PERIODICITY_SL4
=
4
,
NFAPI_NR_SS_PERIODICITY_SL5
=
5
,
NFAPI_NR_SS_PERIODICITY_SL8
=
8
,
NFAPI_NR_SS_PERIODICITY_SL10
=
10
,
NFAPI_NR_SS_PERIODICITY_SL16
=
16
,
NFAPI_NR_SS_PERIODICITY_SL20
=
20
,
NFAPI_NR_SS_PERIODICITY_SL40
=
40
,
NFAPI_NR_SS_PERIODICITY_SL80
=
80
,
NFAPI_NR_SS_PERIODICITY_SL160
=
160
,
NFAPI_NR_SS_PERIODICITY_SL320
=
320
,
NFAPI_NR_SS_PERIODICITY_SL640
=
640
,
NFAPI_NR_SS_PERIODICITY_SL1280
=
1280
,
NFAPI_NR_SS_PERIODICITY_SL2560
=
2560
}
nfapi_nr_search_space_monitoring_periodicity_e
;
typedef
enum
{
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_A
=
0
,
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_B
,
...
...
@@ -496,9 +525,9 @@ typedef struct{
uint8_t
css_format_2_2
;
uint8_t
css_format_2_3
;
uint8_t
uss_dci_formats
;
uint
8
_t
srs_monitoring_periodicity
;
uint
8
_t
slot_monitoring_periodicity
;
uint
8
_t
slot_monitoring_offset
;
uint
16
_t
srs_monitoring_periodicity
;
uint
16
_t
slot_monitoring_periodicity
;
uint
16
_t
slot_monitoring_offset
;
uint16_t
monitoring_symbols_in_slot
;
uint16_t
number_of_candidates
[
NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS
];
}
nfapi_nr_search_space_t
;
...
...
@@ -516,7 +545,7 @@ typedef struct {
uint8_t
aggregation_level
;
uint8_t
n_rb
;
uint8_t
n_symb
;
u
int8_t
rb_offset
;
int8_t
rb_offset
;
uint8_t
cr_mapping_type
;
uint8_t
reg_bundle_size
;
uint8_t
interleaver_size
;
...
...
openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c
View file @
be5f62a9
...
...
@@ -1160,7 +1160,6 @@ uint32_t polar_decoder_int16(int16_t *input,
out
[
0
]
=
Ar
;
return
(
crc
^
rxcrc
);
...
...
openair1/PHY/MODULATION/slot_fep_nr.c
View file @
be5f62a9
...
...
@@ -54,13 +54,19 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
//int i;
unsigned
int
frame_length_samples
=
frame_parms
->
samples_per_subframe
*
10
;
unsigned
int
rx_offset
;
NR_UE_PDCCH
*
pdcch_vars
=
ue
->
pdcch_vars
[
ue
->
current_thread_id
[
Ns
>>
1
]][
0
];
uint16_t
coreset_start_subcarrier
=
frame_parms
->
first_carrier_offset
+
((
int
)
floor
(
frame_parms
->
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
)
+
pdcch_vars
->
coreset
[
0
].
rb_offset
)
*
NR_NB_SC_PER_RB
;
uint16_t
nb_rb_coreset
=
24
;
uint16_t
bwp_start_subcarrier
=
frame_parms
->
first_carrier_offset
+
516
;
NR_UE_PDCCH
*
pdcch_vars
=
ue
->
pdcch_vars
[
ue
->
current_thread_id
[
Ns
]][
0
];
uint16_t
coreset_start_subcarrier
=
frame_parms
->
first_carrier_offset
;
//
+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
uint16_t
nb_rb_coreset
=
0
;
uint16_t
bwp_start_subcarrier
=
frame_parms
->
first_carrier_offset
;
//
+516;
uint16_t
nb_rb_pdsch
=
50
;
uint8_t
p
=
0
;
uint8_t
l0
=
2
;
uint8_t
l0
=
pdcch_vars
->
coreset
[
0
].
duration
;
uint64_t
coreset_freq_dom
=
pdcch_vars
->
coreset
[
0
].
frequencyDomainResources
;
for
(
int
i
=
0
;
i
<
45
;
i
++
)
{
if
(((
coreset_freq_dom
&
0x1FFFFFFFFFFF
)
>>
i
)
&
0x1
)
nb_rb_coreset
++
;
}
nb_rb_coreset
=
6
*
nb_rb_coreset
;
//printf("corset duration %d nb_rb_coreset %d\n", l0, nb_rb_coreset);
void
(
*
dft
)(
int16_t
*
,
int16_t
*
,
int
);
int
tmp_dft_in
[
8192
]
__attribute__
((
aligned
(
32
)));
// This is for misalignment issues for 6 and 15 PRBs
...
...
@@ -104,9 +110,9 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
}
if
(
no_prefix
)
{
slot_offset
=
frame_parms
->
ofdm_symbol_size
*
(
frame_parms
->
symbols_per_slot
*
frame_parms
->
slots_per_subframe
)
*
(
Ns
>>
1
);
slot_offset
=
frame_parms
->
ofdm_symbol_size
*
(
frame_parms
->
symbols_per_slot
)
*
(
Ns
);
}
else
{
slot_offset
=
(
frame_parms
->
samples_per_s
ubframe
)
*
(
Ns
>>
1
);
slot_offset
=
(
frame_parms
->
samples_per_s
lot
)
*
(
Ns
);
}
/*if (l<0 || l>=7-frame_parms->Ncp) {
...
...
@@ -122,7 +128,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
for
(
aa
=
0
;
aa
<
frame_parms
->
nb_antennas_rx
;
aa
++
)
{
memset
(
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
0
,
frame_parms
->
ofdm_symbol_size
*
sizeof
(
int
));
memset
(
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
0
,
frame_parms
->
ofdm_symbol_size
*
sizeof
(
int
));
rx_offset
=
sample_offset
+
slot_offset
+
nb_prefix_samples0
-
SOFFSET
;
// Align with 256 bit
...
...
@@ -130,7 +136,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
#ifdef DEBUG_FEP
// if (ue->frame <100)
/*LOG_I(PHY,*/
printf
(
"slot_fep: frame %d: slot %d, symbol %d, nb_prefix_samples %d, nb_prefix_samples0 %d, slot_offset %d, sample_offset %d,rx_offset %d, frame_length_samples %d
\n
"
,
ue
->
proc
.
proc_rxtx
[(
Ns
>>
1
)
&
1
].
frame_rx
,
Ns
,
symbol
,
/*LOG_I(PHY,*/
printf
(
"slot_fep: frame %d: slot %d, symbol %d, nb_prefix_samples %d, nb_prefix_samples0 %d, slot_offset %d,
sample_offset %d,rx_offset %d, frame_length_samples %d
\n
"
,
ue
->
proc
.
proc_rxtx
[(
Ns
)
&
1
].
frame_rx
,
Ns
,
symbol
,
nb_prefix_samples
,
nb_prefix_samples0
,
slot_offset
,
sample_offset
,
rx_offset
,
frame_length_samples
);
#endif
...
...
@@ -146,14 +152,14 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
(
void
*
)
&
common_vars
->
rxdata
[
aa
][
rx_offset
%
frame_length_samples
],
frame_parms
->
ofdm_symbol_size
*
sizeof
(
int
));
dft
((
int16_t
*
)
tmp_dft_in
,
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
}
else
{
// use dft input from RX buffer directly
#if UE_TIMING_TRACE
start_meas
(
&
ue
->
rx_dft_stats
);
#endif
dft
((
int16_t
*
)
&
common_vars
->
rxdata
[
aa
][(
rx_offset
)
%
frame_length_samples
],
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
#if UE_TIMING_TRACE
stop_meas
(
&
ue
->
rx_dft_stats
);
#endif
...
...
@@ -175,11 +181,11 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
(
void
*
)
&
common_vars
->
rxdata
[
aa
][(
rx_offset
)
%
frame_length_samples
],
frame_parms
->
ofdm_symbol_size
*
sizeof
(
int
));
dft
((
int16_t
*
)
tmp_dft_in
,
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
}
else
{
// use dft input from RX buffer directly
dft
((
int16_t
*
)
&
common_vars
->
rxdata
[
aa
][(
rx_offset
)
%
frame_length_samples
],
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
(
int16_t
*
)
&
common_vars
->
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
[
aa
][
frame_parms
->
ofdm_symbol_size
*
symbol
],
1
);
}
#if UE_TIMING_TRACE
stop_meas
(
&
ue
->
rx_dft_stats
);
...
...
openair1/PHY/NR_REFSIG/nr_dmrs_rx.c
View file @
be5f62a9
...
...
@@ -32,6 +32,7 @@
//#define NR_PBCH_DMRS_LENGTH_DWORD 5
//#define NR_PBCH_DMRS_LENGTH 144
//#define DEBUG_PDCCH
#include
"refsig_defs_ue.h"
#include
"PHY/defs_nr_UE.h"
...
...
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @
be5f62a9
...
...
@@ -20,7 +20,7 @@
*/
/*! \file PHY/NR_TRANSPORT/nr_dci.c
* \brief Implements DCI encoding and PDCCH TX procedures (38.212/38.213/38.214). V15.
2
.0 201
8
-0
6
.
* \brief Implements DCI encoding and PDCCH TX procedures (38.212/38.213/38.214). V15.
4
.0 201
9
-0
1
.
* \author Guy De Souza
* \date 2018
* \version 0.1
...
...
@@ -35,7 +35,6 @@
//#define DEBUG_PDCCH_DMRS
//#define DEBUG_DCI
//#define DEBUG_CHANNEL_CODING
#define PDCCH_TEST_POLAR_TEMP_FIX
extern
short
nr_mod_table
[
NR_MOD_TABLE_SIZE_SHORT
];
...
...
@@ -154,7 +153,7 @@ void nr_pdcch_scrambling(uint32_t *in,
}
}
(
*
out
)
^=
((((
*
in
)
>>
(
i
&
0x1f
))
&
1
)
^
((
s
>>
(
i
&
0x1f
))
&
1
))
<<
(
i
&
0x1f
);
//
printf("nr_pdcch_scrambling: in %d => out %d\n",((*in)>>(i&0x1f))&1,((*out)>>(i&0x1f))&1);
//
printf("nr_pdcch_scrambling: in %d
seq 0x%08x
=> out %d\n",((*in)>>(i&0x1f))&1,
s,
((*out)>>(i&0x1f))&1);
}
}
...
...
@@ -169,8 +168,10 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
{
int16_t
mod_dmrs
[
NR_MAX_CSET_DURATION
][
NR_MAX_PDCCH_DMRS_LENGTH
>>
1
];
// 3 for the max coreset duration
uint8_t
idx
=
0
;
//uint16_t a;
uint32_t
dmrs_seq
[
NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD
];
uint16_t
dmrs_offset
=
0
;
uint16_t
cset_start_sc
;
uint8_t
cset_start_symb
,
cset_nsymb
;
int
k
,
l
,
k_prime
,
dci_idx
,
dmrs_idx
;
nr_cce_t
cce
;
nr_reg_t
reg
;
...
...
@@ -179,62 +180,88 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
/*First iteration: single DCI*/
NR_gNB_DCI_ALLOC_t
dci_alloc
=
pdcch_vars
.
dci_alloc
[
0
];
nfapi_nr_dl_config_pdcch_parameters_rel15_t
pdcch_params
=
dci_alloc
.
pdcch_params
;
uint16_t
dmrs_length
=
dci_alloc
.
L
*
36
;
//2(QPSK)*3(per RB)*6(REG per CCE)
uint16_t
encoded_length
=
dci_alloc
.
L
*
108
;
//2(QPSK)*9(per RB)*6(REG per CCE)
/*The coreset is initialised
* in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset
* in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0
* or the rb_offset for other coresets
* in time: by its first slot and its first symbol*/
uint16_t
cset_start_sc
=
frame_parms
.
first_carrier_offset
+
((
int
)
floor
(
frame_parms
.
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
)
+
pdcch_params
.
rb_offset
)
*
NR_NB_SC_PER_RB
;
// uint8_t cset_start_symb = pdcch_params.first_slot*frame_parms.symbols_per_slot + pdcch_params.first_symbol;
uint8_t
cset_start_symb
=
pdcch_params
.
first_symbol
;
uint8_t
cset_nsymb
=
pdcch_params
.
n_symb
;
if
(
pdcch_params
.
config_type
==
NFAPI_NR_CSET_CONFIG_MIB_SIB1
){
cset_start_sc
=
frame_parms
.
first_carrier_offset
+
(
frame_parms
.
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
+
pdcch_params
.
rb_offset
)
*
NR_NB_SC_PER_RB
;
}
else
cset_start_sc
=
frame_parms
.
first_carrier_offset
+
pdcch_params
.
rb_offset
*
NR_NB_SC_PER_RB
;
cset_start_symb
=
pdcch_params
.
first_symbol
;
cset_nsymb
=
pdcch_params
.
n_symb
;
dci_idx
=
0
;
LOG_I
(
PHY
,
"Coreset starting subcarrier %d on symbol %d (%d symbols)
\n
"
,
cset_start_sc
,
cset_start_symb
,
cset_nsymb
);
// DMRS length is per OFDM symbol
uint16_t
dmrs_length
=
(
pdcch_params
.
precoder_granularity
==
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
)
?
(
pdcch_params
.
n_rb
*
6
)
:
(
dci_alloc
.
L
*
36
/
cset_nsymb
);
//2(QPSK)*3(per RB)*6(REG per CCE)
uint16_t
encoded_length
=
dci_alloc
.
L
*
108
;
//2(QPSK)*9(per RB)*6(REG per CCE)
LOG_I
(
PHY
,
"DMRS length per symbol %d
\t
DCI encoded length %d
\n
"
,
dmrs_length
,
encoded_length
);
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if
(
pdcch_params
.
config_type
==
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
)
gold_pdcch_dmrs
+=
((
int
)
floor
(
frame_parms
.
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
)
+
pdcch_params
.
rb_offset
)
*
3
/
32
;
if
(
pdcch_params
.
config_type
==
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
)
{
for
(
int
symb
=
cset_start_symb
;
symb
<
cset_start_symb
+
pdcch_params
.
n_symb
;
symb
++
)
gold_pdcch_dmrs
[
symb
]
+=
(
pdcch_params
.
rb_offset
*
3
)
>>
5
;
dmrs_offset
=
(
pdcch_params
.
rb_offset
*
3
)
&
0x1f
;
LOG_I
(
PHY
,
"PDCCH DMRS offset %d
\n
"
,
dmrs_offset
);
}
for
(
int
symb
=
cset_start_symb
;
symb
<
cset_start_symb
+
pdcch_params
.
n_symb
;
symb
++
)
{
for
(
int
i
=
0
;
i
<
dmrs_length
>>
1
;
i
++
)
{
idx
=
((((
gold_pdcch_dmrs
[
symb
][(
i
<<
1
)
>>
5
])
>>
((
i
<<
1
)
&
0x1f
))
&
1
)
<<
1
)
^
(((
gold_pdcch_dmrs
[
symb
][((
i
<<
1
)
+
1
)
>>
5
])
>>
(((
i
<<
1
)
+
1
)
&
0x1f
))
&
1
);
mod_dmrs
[
symb
][
i
<<
1
]
=
nr_mod_table
[(
NR_MOD_TABLE_QPSK_OFFSET
+
idx
)
<<
1
];
mod_dmrs
[
symb
][(
i
<<
1
)
+
1
]
=
nr_mod_table
[((
NR_MOD_TABLE_QPSK_OFFSET
+
idx
)
<<
1
)
+
1
];
#ifdef DEBUG_PDCCH_DMRS
printf
(
"symb %d i %d idx %d gold seq %u b0-b1 %d-%d mod_dmrs %d %d
\n
"
,
symb
,
i
,
idx
,
gold_pdcch_dmrs
[
symb
][(
i
<<
1
)
>>
5
],
(((
gold_pdcch_dmrs
[
symb
][(
i
<<
1
)
>>
5
])
>>
((
i
<<
1
)
&
0x1f
))
&
1
),
(((
gold_pdcch_dmrs
[
symb
][((
i
<<
1
)
+
1
)
>>
5
])
>>
(((
i
<<
1
)
+
1
)
&
0x1f
))
&
1
),
mod_dmrs
[
symb
][(
i
<<
1
)],
mod_dmrs
[
symb
][(
i
<<
1
)
+
1
]);
#endif
if
(
dmrs_offset
)
{
// a non zero offset requires the DMRS sequence to be rearranged
memset
(
dmrs_seq
,
0
,
NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD
*
sizeof
(
uint32_t
));
for
(
int
i
=
0
;
i
<
dmrs_length
;
i
++
)
{
dmrs_seq
[(
i
>>
5
)]
|=
((
gold_pdcch_dmrs
[
symb
][(
i
+
dmrs_offset
)
>>
5
]
>>
((
i
+
dmrs_offset
)
&
0x1f
))
&
1
)
<<
(
i
&
0x1f
);
#ifdef DEBUG_PDCCH_DMRS
//printf("out 0x%08x in 0x%08x \n", dmrs_seq[(i>>5)], gold_pdcch_dmrs[symb][(i+dmrs_offset)>>5]);
#endif
}
nr_modulation
(
dmrs_seq
,
dmrs_length
,
MOD_QPSK
,
mod_dmrs
[
symb
]);
}
else
nr_modulation
(
gold_pdcch_dmrs
[
symb
],
dmrs_length
,
MOD_QPSK
,
mod_dmrs
[
symb
]);
#ifdef DEBUG_PDCCH_DMRS
for
(
int
i
=
0
;
i
<
dmrs_length
>>
1
;
i
++
)
if
(
dmrs_offset
)
printf
(
"symb %d i %d gold seq 0x%08x mod_dmrs %d %d
\n
"
,
symb
,
i
,
dmrs_seq
[
i
>>
5
],
mod_dmrs
[
symb
][
i
<<
1
],
mod_dmrs
[
symb
][(
i
<<
1
)
+
1
]
);
else
printf
(
"symb %d i %d gold seq 0x%08x mod_dmrs %d %d
\n
"
,
symb
,
i
,
gold_pdcch_dmrs
[
symb
][
i
>>
5
],
mod_dmrs
[
symb
][
i
<<
1
],
mod_dmrs
[
symb
][(
i
<<
1
)
+
1
]
);
#endif
}
/// DCI payload processing
// CRC attachment + Scrambling + Channel coding + Rate matching
uint32_t
encoder_output
[
NR_MAX_DCI_SIZE_DWORD
];
uint16_t
n_RNTI
=
(
pdcch_params
.
search_space_type
==
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
)
?
((
pdcch_params
.
scrambling_id
)
?
pdcch_params
.
rnti
:
0
)
:
0
;
uint16_t
Nid
=
(
pdcch_params
.
search_space_type
==
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
)
?
pdcch_params
.
scrambling_id
:
config
.
sch_config
.
physical_cell_id
.
value
;
//#ifdef PDCCH_TEST_POLAR_TEMP_FIX
// nr_polar_init(¤tPtr, NR_POLAR_DCI_MESSAGE_TYPE, dci_alloc.size, dci_alloc.L);
// t_nrPolar_paramsPtr currentPtr = nr_polar_params(*nrPolar_params, NR_POLAR_DCI_MESSAGE_TYPE, dci_alloc.size, dci_alloc.L);
//#else
uint16_t
n_RNTI
=
(
pdcch_params
.
search_space_type
==
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
)
?
pdcch_params
.
rnti
:
0
;
uint16_t
Nid
=
(
pdcch_params
.
search_space_type
==
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
)
?
pdcch_params
.
scrambling_id
:
config
.
sch_config
.
physical_cell_id
.
value
;
nr_polar_init
(
nrPolar_params
,
NR_POLAR_DCI_MESSAGE_TYPE
,
dci_alloc
.
size
,
dci_alloc
.
L
);
t_nrPolar_paramsPtr
currentPtr
=
nr_polar_params
(
*
nrPolar_params
,
NR_POLAR_DCI_MESSAGE_TYPE
,
dci_alloc
.
size
,
dci_alloc
.
L
);
//#endif
//polar_encoder_dci(dci_alloc.dci_pdu, encoder_output, currentPtr, pdcch_params.rnti);
polar_encoder_fast
(
dci_alloc
.
dci_pdu
,
encoder_output
,
pdcch_params
.
rnti
,
currentPtr
);
#ifdef DEBUG_CHANNEL_CODING
printf
(
"polar rnti %d
\n
"
,
pdcch_params
.
rnti
);
for
(
int
i
=
0
;
i
<
54
;
i
++
)
printf
(
"Encoded Payload: [%d]->0x%08x
\n
"
,
i
,
encoder_output
[
i
]);
printf
(
"
DCI PDU: [0]->0x%08x
\t
[1]->0x%08x
\t
[2]->0x%08x
\t
[3]->0x%08x
\n
"
,
dci_alloc
.
dci_pdu
[
0
],
dci_alloc
.
dci_pdu
[
1
],
dci_alloc
.
dci_pdu
[
2
],
dci_alloc
.
dci_pdu
[
3
]);
printf
(
"
Encoded Payload: [0]->0x%08x
\t
[1]->0x%08x
\t
[2]->0x%08x
\t
[3]->0x%08x
\n
"
,
encoder_output
[
0
],
encoder_output
[
1
],
encoder_output
[
2
],
encoder_output
[
3
]
);
printf
(
"DCI PDU: [0]->0x%lx
\t
[1]->0x%lx
\n
"
,
dci_alloc
.
dci_pdu
[
0
],
dci_alloc
.
dci_pdu
[
1
]);
printf
(
"
Encoded Payload (length:%d dwords):
\n
"
,
encoded_length
>>
5
);
for
(
int
i
=
0
;
i
<
encoded_length
>>
5
;
i
++
)
printf
(
"
[%d]->0x%08x
\t
"
,
i
,
encoder_output
[
i
]);
printf
(
"
\n
"
);
#endif
/// Scrambling
...
...
@@ -247,17 +274,13 @@ printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%0
scrambled_output
[
6
],
scrambled_output
[
7
],
scrambled_output
[
8
],
scrambled_output
[
9
],
scrambled_output
[
10
],
scrambled_output
[
11
]
);
#endif
// QPSK modulation
/
// QPSK modulation
int16_t
mod_dci
[
NR_MAX_DCI_SIZE
>>
1
];
for
(
int
i
=
0
;
i
<
encoded_length
>>
1
;
i
++
)
{
idx
=
((((
scrambled_output
[(
i
<<
1
)
>>
5
])
>>
((
i
<<
1
)
&
0x1f
))
&
1
)
<<
1
)
^
(((
scrambled_output
[((
i
<<
1
)
+
1
)
>>
5
])
>>
(((
i
<<
1
)
+
1
)
&
0x1f
))
&
1
);
mod_dci
[
i
<<
1
]
=
nr_mod_table
[(
NR_MOD_TABLE_QPSK_OFFSET
+
idx
)
<<
1
];
mod_dci
[(
i
<<
1
)
+
1
]
=
nr_mod_table
[((
NR_MOD_TABLE_QPSK_OFFSET
+
idx
)
<<
1
)
+
1
];
nr_modulation
(
scrambled_output
,
encoded_length
,
MOD_QPSK
,
mod_dci
);
#ifdef DEBUG_DCI
printf
(
"i %d idx %d b0-b1 %d-%d mod_dci %d %d
\n
"
,
i
,
idx
,
(((
scrambled_output
[(
i
<<
1
)
>>
5
])
>>
((
i
<<
1
)
&
0x1f
))
&
1
),
(((
scrambled_output
[((
i
<<
1
)
+
1
)
>>
5
])
>>
(((
i
<<
1
)
+
1
)
&
0x1f
))
&
1
)
,
mod_dci
[
(
i
<<
1
)
],
mod_dci
[(
i
<<
1
)
+
1
]);
for
(
int
i
=
0
;
i
<
encoded_length
>>
1
;
i
++
)
printf
(
"i %d mod_dci %d %d
\n
"
,
i
,
mod_dci
[
i
<<
1
],
mod_dci
[(
i
<<
1
)
+
1
]
);
#endif
}
/// Resource mapping
...
...
@@ -289,10 +312,11 @@ printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%0
dmrs_idx
=
0
;
k
=
cset_start_sc
+
1
;
while
(
dmrs_idx
<
3
*
pdcch_params
.
n_rb
)
{
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
amp
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
(
amp
>>
1
)
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
(
amp
>>
1
)
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
#ifdef DEBUG_PDCCH_DMRS
printf
(
"symbol %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
[
aa
])[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
,
((
int16_t
*
)
txdataF
[
aa
])[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
printf
(
"symbol %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
,
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
#endif
k
+=
4
;
if
(
k
>=
frame_parms
.
ofdm_symbol_size
)
...
...
@@ -315,19 +339,23 @@ printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%0
for
(
int
m
=
0
;
m
<
NR_NB_SC_PER_RB
;
m
++
)
{
if
(
m
==
(
k_prime
<<
2
)
+
1
)
{
// DMRS if not already mapped
if
(
pdcch_params
.
precoder_granularity
==
NFAPI_NR_CSET_SAME_AS_REG_BUNDLE
)
{
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
amp
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
(
amp
>>
1
)
*
mod_dmrs
[
l
][
dmrs_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
(
amp
>>
1
)
*
mod_dmrs
[
l
][(
dmrs_idx
<<
1
)
+
1
])
>>
15
;
#ifdef DEBUG_PDCCH_DMRS
printf
(
"l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
[
aa
])[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
,
((
int16_t
*
)
txdataF
[
aa
])[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
printf
(
"l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
,
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
#endif
k_prime
++
;
dmrs_idx
++
;
}
k_prime
++
;
}
else
{
// DCI payload
((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
=
(
amp
*
mod_dci
[
dci_idx
<<
1
])
>>
15
;
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]
=
(
amp
*
mod_dci
[(
dci_idx
<<
1
)
+
1
])
>>
15
;
//printf("dci output %d %d\n",(a * mod_dci[dci_idx<<1]) >> 15, (a * mod_dci[(dci_idx<<1) + 1]) >> 15);
#ifdef DEBUG_DCI
printf
(
"l %d position %d => (%d,%d)
\n
"
,
l
,
k
,((
int16_t
*
)
txdataF
)[(
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
]
,
((
int16_t
*
)
txdataF
)[((
l
*
frame_parms
.
ofdm_symbol_size
+
k
)
<<
1
)
+
1
]);
#endif
dci_idx
++
;
}
k
++
;
...
...
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
View file @
be5f62a9
...
...
@@ -61,11 +61,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
else
{
//NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
}
uint8_t
cond
=
N_reg
%
(
bsize
*
R
);
AssertFatal
(
cond
==
0
,
"CCE to REG interleaving: Invalid configuration leading to non integer C
\n
"
);
C
=
N_reg
/
(
bsize
*
R
);
if
(
pdcch_params
->
cr_mapping_type
==
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED
)
{
AssertFatal
((
N_reg
%
(
bsize
*
R
))
==
0
,
"CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %d, bsize %d R %d)
\n
"
,
N_reg
,
bsize
,
R
);
C
=
N_reg
/
(
bsize
*
R
);
}
tmp
=
L
*
((
Y
+
(
m
*
N_cce
)
/
(
L
*
M_s_max
)
+
n_CI
)
%
(
N_cce
/
L
));
tmp
=
L
*
((
Y
+
(
m
*
N_cce
)
/
(
L
*
M_s_max
)
+
n_CI
)
%
CEILIDIV
(
N_cce
,
L
));
LOG_I
(
PHY
,
"CCE list generation for candidate %d: bundle size %d ilv size %d tmp %d
\n
"
,
m
,
bsize
,
R
,
tmp
);
for
(
uint8_t
cce_idx
=
0
;
cce_idx
<
L
;
cce_idx
++
)
{
...
...
@@ -189,14 +191,16 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
#endif
break
;
case
NFAPI_NR_RNTI_C
:
case
NFAPI_NR_RNTI_C
:
// indicating a DL DCI format 1bit
pos
++
;
*
dci_pdu
|=
(
pdu_rel15
->
format_indicator
&
1
)
<<
(
dci_alloc
->
size
-
pos
);
// Freq domain assignment (275rb >> fsize = 16)
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
pos
+=
fsize
;
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_alloc
->
size
-
pos
));
if
(((
pdu_rel15
->
frequency_domain_assignment
+
1
)
&
1
)
==
0
)
//fsize are all 1 38.212 p86
{
...
...
@@ -223,8 +227,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// Time domain assignment 4bit
pos
+=
4
;
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
&
0xf
)
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
&
0xf
)
<<
(
dci_alloc
->
size
-
pos
));
// VRB to PRB mapping 1bit
pos
++
;
...
...
@@ -244,7 +247,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// HARQ process number 4bit
pos
+=
4
;
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
&
0xf
)
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
&
0xf
)
<<
(
dci_alloc
->
size
-
pos
));
// Downlink assignment index 2bit
pos
+=
2
;
...
...
@@ -252,15 +255,15 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// TPC command for scheduled PUCCH 2bit
pos
+=
2
;
*
dci_pdu
|=
((
pdu_rel15
->
tpc
&
3
)
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
tpc
&
3
)
<<
(
dci_alloc
->
size
-
pos
));
// PUCCH resource indicator 3bit
pos
+=
3
;
*
dci_pdu
|=
((
pdu_rel15
->
pucch_resource_indicator
&
0x7
)
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
pucch_resource_indicator
&
0x7
)
<<
(
dci_alloc
->
size
-
pos
));
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos
+=
3
;
*
dci_pdu
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
&
0x7
)
<<
(
dci_alloc
->
size
-
pos
));
*
dci_pdu
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
&
0x7
)
<<
(
dci_alloc
->
size
-
pos
));
}
//end else
break
;
...
...
openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
View file @
be5f62a9
...
...
@@ -28,6 +28,7 @@
#include
"PHY/NR_REFSIG/refsig_defs_ue.h"
#include
"filt16a_32.h"
#include
"T.h"
//#define DEBUG_PDSCH
//#define DEBUG_PDCCH
...
...
@@ -271,8 +272,8 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t
nushift
;
int
**
dl_ch_estimates
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
dl_ch_estimates
[
eNB_offset
];
int
**
rxdataF
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
;
int
**
dl_ch_estimates
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
dl_ch_estimates
[
eNB_offset
];
int
**
rxdataF
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
;
nushift
=
1
;
ue
->
frame_parms
.
nushift
=
nushift
;
...
...
@@ -287,7 +288,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
k
=
coreset_start_subcarrier
;
#ifdef DEBUG_PDCCH
printf
(
"PDCCH Channel Estimation : ThreadId %d, eNB_offset %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d
\n
"
,
ue
->
current_thread_id
[
Ns
>>
1
],
eNB_offset
,
ch_offset
,
ue
->
frame_parms
.
ofdm_symbol_size
,
printf
(
"PDCCH Channel Estimation : ThreadId %d, eNB_offset %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d
\n
"
,
ue
->
current_thread_id
[
Ns
],
eNB_offset
,
ch_offset
,
ue
->
frame_parms
.
ofdm_symbol_size
,
ue
->
frame_parms
.
Ncp
,
l
,
Ns
,
k
,
symbol
);
#endif
...
...
@@ -297,7 +298,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
// generate pilot
nr_pdcch_dmrs_rx
(
ue
,
eNB_offset
,
Ns
,
ue
->
nr_gold_pdcch
[
eNB_offset
][
Ns
>>
1
][
symbol
],
&
pilot
[
0
],
2000
,
nb_rb_coreset
);
nr_pdcch_dmrs_rx
(
ue
,
eNB_offset
,
Ns
,
ue
->
nr_gold_pdcch
[
eNB_offset
][
Ns
][
symbol
],
&
pilot
[
0
],
2000
,
nb_rb_coreset
);
for
(
aarx
=
0
;
aarx
<
ue
->
frame_parms
.
nb_antennas_rx
;
aarx
++
)
{
...
...
@@ -459,16 +460,16 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
break
;
}
//
if( (Ns==
2
) && (l == 0))
if
(
(
Ns
==
1
)
&&
(
l
==
0
))
{
// do ifft of channel estimate
for
(
aarx
=
0
;
aarx
<
ue
->
frame_parms
.
nb_antennas_rx
;
aarx
++
)
for
(
p
=
0
;
p
<
ue
->
frame_parms
.
nb_antenna_ports_eNB
;
p
++
)
{
if
(
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
dl_ch_estimates
[
eNB_offset
][(
p
<<
1
)
+
aarx
])
if
(
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
dl_ch_estimates
[
eNB_offset
][(
p
<<
1
)
+
aarx
])
{
LOG_D
(
PHY
,
"Channel Impulse Computation Slot %d ThreadId %d Symbol %d
\n
"
,
Ns
,
ue
->
current_thread_id
[
Ns
>>
1
],
l
);
idft
((
int16_t
*
)
&
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
dl_ch_estimates
[
eNB_offset
][(
p
<<
1
)
+
aarx
][
0
],
(
int16_t
*
)
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
dl_ch_estimates_time
[
eNB_offset
][(
p
<<
1
)
+
aarx
],
1
);
LOG_D
(
PHY
,
"Channel Impulse Computation Slot %d ThreadId %d Symbol %d
\n
"
,
Ns
,
ue
->
current_thread_id
[
Ns
],
l
);
idft
((
int16_t
*
)
&
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
dl_ch_estimates
[
eNB_offset
][(
p
<<
1
)
+
aarx
][
0
],
(
int16_t
*
)
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
dl_ch_estimates_time
[
eNB_offset
][(
p
<<
1
)
+
aarx
],
1
);
}
}
}
...
...
@@ -496,8 +497,8 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t
nushift
;
int
**
dl_ch_estimates
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
dl_ch_estimates
[
eNB_offset
];
int
**
rxdataF
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
>>
1
]].
rxdataF
;
int
**
dl_ch_estimates
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
dl_ch_estimates
[
eNB_offset
];
int
**
rxdataF
=
ue
->
common_vars
.
common_vars_rx_data_per_thread
[
ue
->
current_thread_id
[
Ns
]].
rxdataF
;
nushift
=
(
p
>>
1
)
&
1
;
ue
->
frame_parms
.
nushift
=
nushift
;
...
...
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @
be5f62a9
...
...
@@ -805,7 +805,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
// For each BWP the number of CORESETs is limited to 3 (including initial CORESET Id=0 -> ControlResourceSetId (0..maxNrofControlReourceSets-1) (0..12-1)
//uint32_t n_BWP_start = 0;
//uint32_t n_rb_offset = 0;
uint32_t
n_rb_offset
=
pdcch_vars2
->
coreset
[
nb_coreset_active
].
rb_offset
+
(
int
)
floor
(
frame_parms
->
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
);
uint32_t
n_rb_offset
=
pdcch_vars2
->
coreset
[
nb_coreset_active
].
rb_offset
/*
+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)
*/
;
// start time position for CORESET
// parameter symbol_mon is a 14 bits bitmap indicating monitoring symbols within a slot
uint8_t
start_symbol
=
0
;