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160 results
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with 729 additions and 1326 deletions
......@@ -47,6 +47,7 @@
#include "openair1/SIMULATION/RF/rf.h"
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h"
//#define DEBUG_NR_DLSCHSIM
......@@ -430,13 +431,10 @@ int main(int argc, char **argv)
NR_gNB_DLSCH_t *dlsch = msgDataTx.dlsch[0][0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_process.pdsch_pdu.pdsch_pdu_rel15;
//time_stats_t *rm_stats, *te_stats, *i_stats;
uint8_t is_crnti = 0, llr8_flag = 0;
uint8_t is_crnti = 0;
unsigned int TBS = 8424;
unsigned int available_bits;
uint8_t nb_re_dmrs = 6; // No data in dmrs symbol
uint16_t length_dmrs = 1;
unsigned char mod_order;
uint16_t rate;
uint8_t Nl = 1;
uint8_t rvidx = 0;
dlsch->rnti = 1;
......@@ -444,9 +442,9 @@ int main(int argc, char **argv)
dlsch->harq_processes[0]->rvidx = rvidx;*/
//printf("dlschsim harqid %d nb_rb %d, mscs %d\n",dlsch->harq_ids[subframe],
// dlsch->harq_processes[0]->nb_rb,dlsch->harq_processes[0]->mcs,dlsch->harq_processes[0]->Nl);
mod_order = nr_get_Qm_dl(Imcs, mcs_table);
rate = nr_get_code_rate_dl(Imcs, mcs_table);
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
unsigned char mod_order = nr_get_Qm_dl(Imcs, mcs_table);
uint16_t rate = nr_get_code_rate_dl(Imcs, mcs_table);
unsigned int available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl);
printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order);
//dlsch->harq_ids[subframe]= 0;
......@@ -478,6 +476,7 @@ int main(int argc, char **argv)
harq_process->Qm = mod_order;
harq_process->rvidx = rvidx;
harq_process->R = rate;
harq_process->TBS = TBS;
harq_process->dmrsConfigType = NFAPI_NR_DMRS_TYPE1;
harq_process->dlDmrsSymbPos = 4;
harq_process->n_dmrs_cdm_groups = 1;
......@@ -498,8 +497,8 @@ int main(int argc, char **argv)
//printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32));
// generate signal
unsigned char output[rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS] __attribute__((aligned(32)));
bzero(output,rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS);
unsigned char output[rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS] __attribute__((aligned(32)));
bzero(output,rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS);
if (input_fd == NULL) {
nr_dlsch_encoding(gNB, frame, slot, &dlsch->harq_process, frame_parms,output,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
}
......@@ -551,7 +550,7 @@ int main(int argc, char **argv)
ret = nr_dlsch_decoding(UE, &proc, 0, channel_output_fixed, &UE->frame_parms,
dlsch0_ue, dlsch0_ue->harq_processes[0], frame, nb_symb_sch,
slot,harq_pid, is_crnti, llr8_flag);
slot,harq_pid, is_crnti);
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DECODING0, VCD_FUNCTION_OUT);
......
......@@ -96,7 +96,6 @@ uint16_t sl_ahead=0;
uint64_t downlink_frequency[MAX_NUM_CCs][4];
THREAD_STRUCT thread_struct;
nfapi_ue_release_request_body_t release_rntis;
uint32_t N_RB_DL = 106;
//Fixme: Uniq dirty DU instance, by global var, datamodel need better management
instance_t DUuniqInstance=0;
instance_t CUuniqInstance=0;
......@@ -270,9 +269,9 @@ int g_mcsIndex = -1, g_mcsTableIdx = 0, g_rbStart = -1, g_rbSize = -1, g_nrOfLay
void nr_dlsim_preprocessor(module_id_t module_id,
frame_t frame,
sub_frame_t slot) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
AssertFatal(UE_info->num_UEs == 1, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[0];
NR_UE_info_t *UE_info = RC.nrmac[module_id]->UE_info.list[0];
AssertFatal(RC.nrmac[module_id]->UE_info.list[1]==NULL, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels[0].ServingCellConfigCommon;
/* manually set free CCE to 0 */
......@@ -282,14 +281,14 @@ void nr_dlsim_preprocessor(module_id_t module_id,
find_aggregation_candidates(&sched_ctrl->aggregation_level,
&nr_of_candidates,
sched_ctrl->search_space,4);
sched_ctrl->coreset = get_coreset(module_id, scc, sched_ctrl->active_bwp->bwp_Dedicated, sched_ctrl->search_space, target_ss);
sched_ctrl->coreset = get_coreset(RC.nrmac[module_id], scc, sched_ctrl->active_bwp->bwp_Dedicated, sched_ctrl->search_space, target_ss);
sched_ctrl->cce_index = 0;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
nr_set_pdsch_semi_static(NULL,
scc,
UE_info->CellGroup[0],
UE_info->CellGroup,
sched_ctrl->active_bwp,
NULL,
/* tda = */ 0,
......@@ -658,7 +657,7 @@ int main(int argc, char **argv)
default:
case 'h':
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n",
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n",
argv[0]);
printf("-h This message\n");
printf("-L <log level, 0(errors), 1(warning), 2(analysis), 3(info), 4(debug), 5(trace)>\n");
......@@ -667,7 +666,7 @@ int main(int argc, char **argv)
printf("-n Number of frames to simulate\n");
printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n");
printf("-S Ending SNR, runs from SNR0 to SNR1\n");
printf("-t Delay spread for multipath channel\n");
//printf("-t Delay spread for multipath channel\n");
printf("-g [A,B,C,D,E,F,G,R] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models or R for MIMO model (ignores delay spread and Ricean factor)\n");
printf("-y Number of TX antennas used in gNB\n");
printf("-z Number of RX antennas used in UE\n");
......@@ -837,8 +836,7 @@ int main(int argc, char **argv)
gNB_mac->pre_processor_dl = nr_dlsim_preprocessor;
phy_init_nr_gNB(gNB,0,1);
N_RB_DL = gNB->frame_parms.N_RB_DL;
NR_UE_info_t *UE_info = &RC.nrmac[0]->UE_info;
UE_info->num_UEs=1;
NR_UE_info_t *UE_info = RC.nrmac[0]->UE_info.list[0];
// stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
......@@ -853,10 +851,14 @@ int main(int argc, char **argv)
double fs,bw;
if (mu == 1 && N_RB_DL == 217) {
if (mu == 0 && N_RB_DL == 25) {
fs = 7.68e6;
bw = 5e6;
}
else if (mu == 1 && N_RB_DL == 217) {
fs = 122.88e6;
bw = 80e6;
}
}
else if (mu == 1 && N_RB_DL == 245) {
fs = 122.88e6;
bw = 90e6;
......@@ -877,6 +879,10 @@ int main(int argc, char **argv)
fs = 61.44e6;
bw = 60e6;
}
else if (mu == 1 && N_RB_DL == 24) {
fs = 15.36e6;
bw = 10e6;
}
else if (mu == 3 && N_RB_DL == 66) {
fs = 122.88e6;
bw = 100e6;
......@@ -1098,10 +1104,10 @@ int main(int argc, char **argv)
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1);
UE_info->UE_sched_ctrl.harq_processes[harq_pid].ndi = !(trial&1);
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].round = round;
UE_info->UE_sched_ctrl.harq_processes[harq_pid].round = round;
for (int i=0; i<MAX_NUM_CORESET; i++)
gNB_mac->pdcch_cand[i] = 0;
......
......@@ -240,7 +240,7 @@ int main(int argc, char **argv){
int i, l, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1;
int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0;
uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format=0;
uint8_t frame = 1, slot=19, slot_gNB=19, config_index = 98, prach_sequence_length = 1, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol;
uint8_t config_index = 98, prach_sequence_length = 1, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol;
uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1;
uint32_t tx_lev = 10000, prach_errors = 0; //,tx_lev_dB;
uint64_t SSB_positions = 0x01;
......@@ -536,7 +536,7 @@ int main(int argc, char **argv){
frame_parms->N_RB_UL = N_RB_UL;
frame_parms->threequarter_fs = threequarter_fs;
frame_parms->frame_type = TDD;
frame_parms->freq_range = (mu==1 ? nr_FR1 : nr_FR2);
frame_parms->freq_range = (mu != 3 ? nr_FR1 : nr_FR2);
frame_parms->numerology_index = mu;
nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions);
......@@ -546,9 +546,11 @@ int main(int argc, char **argv){
frame_parms->numerology_index,
frame_parms->N_RB_UL*(180e3)*(1 << frame_parms->numerology_index));
uint8_t subframe = slot/frame_parms->slots_per_subframe;
uint8_t frame = 1;
uint8_t subframe = 9;
uint8_t slot = 10 * frame_parms->slots_per_subframe - 1;
if (config_index<67 && mu==1) { prach_sequence_length=0; slot = subframe*2; slot_gNB = 1+(subframe*2); }
if (config_index<67 && mu != 3) { prach_sequence_length=0; slot = subframe * frame_parms->slots_per_subframe; }
uint16_t N_ZC = prach_sequence_length == 0 ? 839 : 139;
printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length);
......@@ -569,9 +571,11 @@ int main(int argc, char **argv){
ru->gNB_list[0] = gNB;
gNB->gNB_config.carrier_config.num_tx_ant.value = 1;
gNB->gNB_config.carrier_config.num_rx_ant.value = 1;
if (mu==1)
if (mu == 0)
gNB->gNB_config.tdd_table.tdd_period.value = 7;
else if (mu == 1)
gNB->gNB_config.tdd_table.tdd_period.value = 6;
else if (mu==3)
else if (mu == 3)
gNB->gNB_config.tdd_table.tdd_period.value = 3;
else {
printf("unsupported numerology %d\n",mu);
......@@ -585,7 +589,7 @@ int main(int argc, char **argv){
int ret = get_nr_prach_info_from_index(config_index,
(int)frame,
(int)slot_gNB,
(int)slot,
absoluteFrequencyPointA,
mu,
frame_parms->frame_type,
......@@ -717,12 +721,7 @@ int main(int argc, char **argv){
bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index);
AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n", bw, frame_parms->numerology_index, N_RB_UL);
if (bw <= 30.72e6)
fs = 30.72e6;
else if (bw <= 61.44e6)
fs = 61.44e6;
else if (bw <= 122.88e6)
fs = 122.88e6;
fs = frame_parms->samples_per_subframe * 1e3;
LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES);
......
......@@ -47,6 +47,7 @@
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "common/utils/threadPool/thread-pool.h"
#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h"
//#define DEBUG_NR_ULSCHSIM
......@@ -461,7 +462,7 @@ int main(int argc, char **argv)
rel15_ul->pusch_data.rv_index = rvidx;
rel15_ul->nrOfLayers = Nl;
rel15_ul->target_code_rate = code_rate;
rel15_ul->pusch_data.tb_size = TBS/8;
rel15_ul->pusch_data.tb_size = TBS>>3;
///////////////////////////////////////////////////
double modulated_input[16 * 68 * 384]; // [hna] 16 segments, 68*Zc
......@@ -488,7 +489,9 @@ int main(int argc, char **argv)
harq_process_ul_ue->pusch_pdu.nr_of_symbols = nb_symb_sch;
harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*nb_codewords;
harq_process_ul_ue->pusch_pdu.pusch_data.rv_index = rvidx;
harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS/8;
harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS>>3;
harq_process_ul_ue->pusch_pdu.target_code_rate = code_rate;
harq_process_ul_ue->pusch_pdu.qam_mod_order = mod_order;
unsigned char *test_input = harq_process_ul_ue->a;
///////////
......
......@@ -91,7 +91,6 @@ double cpuf;
uint64_t downlink_frequency[MAX_NUM_CCs][4];
THREAD_STRUCT thread_struct;
nfapi_ue_release_request_body_t release_rntis;
uint32_t N_RB_DL = 106;
//Fixme: Uniq dirty DU instance, by global var, datamodel need better management
instance_t DUuniqInstance=0;
......@@ -306,7 +305,6 @@ int main(int argc, char **argv)
int32_t txlev_sum = 0, atxlev[4];
int start_rb = 0;
int UE_id =0; // [hna] only works for UE_id = 0 because NUMBER_OF_NR_UE_MAX is set to 1 (phy_init_nr_gNB causes segmentation fault)
float target_error_rate = 0.01;
int print_perf = 0;
cpuf = get_cpu_freq_GHz();
int msg3_flag = 0;
......@@ -314,7 +312,7 @@ int main(int argc, char **argv)
float roundStats[100];
double effRate[100];
double effTP[100];
//float eff_tp_check = 0.7;
float eff_tp_check = 0.7;
uint8_t snrRun;
int prb_inter = 0;
......@@ -322,8 +320,8 @@ int main(int argc, char **argv)
int modify_dmrs = 0;
/* L_PTRS = ptrs_arg[0], K_PTRS = ptrs_arg[1] */
int ptrs_arg[2] = {-1,-1};// Invalid values
/* DMRS TYPE = dmrs_arg[0], Add Pos = dmrs_arg[1] */
int dmrs_arg[2] = {-1,-1};// Invalid values
/* mapping type = dmrs_arg[0], Add Pos = dmrs_arg[1], dmrs config type = dmrs_arg[2] */
int dmrs_arg[3] = {-1,-1,-1};// Invalid values
uint16_t ptrsSymPos = 0;
uint16_t ptrsSymbPerSlot = 0;
uint16_t ptrsRePerSymb = 0;
......@@ -350,7 +348,7 @@ int main(int argc, char **argv)
/* initialize the sin-cos table */
InitSinLUT();
while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:i:kl:m:n:p:r:s:u:w:y:z:F:G:H:M:N:PR:S:T:U:L:Z:W:")) != -1) {
while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:ikl:m:n:p:r:s:t:u:w:y:z:F:G:H:M:N:PR:S:T:U:L:Z:W:")) != -1) {
printf("handling optarg %c\n",c);
switch (c) {
......@@ -488,11 +486,10 @@ int main(int argc, char **argv)
start_rb = atoi(optarg);
break;
/*
case 't':
eff_tp_check = (float)atoi(optarg)/100;
break;
*/
/*
case 'r':
ricean_factor = pow(10,-.1*atof(optarg));
......@@ -594,7 +591,7 @@ int main(int argc, char **argv)
default:
case 'h':
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId -Z Enable SC-FDMA in Uplink \n", argv[0]);
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId -Z Enable SC-FDMA in Uplink \n", argv[0]);
//printf("-d Use TDD\n");
printf("-d Introduce delay in terms of number of samples\n");
printf("-f Number of frames to simulate\n");
......@@ -606,7 +603,7 @@ int main(int argc, char **argv)
printf("-m MCS value\n");
printf("-n Number of trials to simulate\n");
printf("-p Use extended prefix mode\n");
printf("-t Delay spread for multipath channel\n");
//printf("-t Delay spread for multipath channel\n");
printf("-u Set the numerology\n");
printf("-w Start PRB for PUSCH\n");
//printf("-x Transmission mode (1,2,6 for the moment)\n");
......@@ -649,16 +646,37 @@ int main(int argc, char **argv)
double sampling_frequency;
double bandwidth;
if (N_RB_UL >= 217) sampling_frequency = 122.88;
else if (N_RB_UL >= 106) sampling_frequency = 61.44;
else if (N_RB_UL >= 32) sampling_frequency = 32.72;
else { printf("Need at least 106 PRBs\b"); exit(-1); }
if (N_RB_UL == 273) bandwidth = 100;
else if (N_RB_UL == 217) bandwidth = 80;
else if (N_RB_UL == 106) bandwidth = 40;
else if (N_RB_UL == 32) bandwidth = 50;
else { printf("Add N_RB_UL %d\n",N_RB_UL); exit(-1); }
if (mu == 0 && N_RB_UL == 25 ) {
sampling_frequency = 7.68;
bandwidth = 5;
}
else if (mu == 1 && N_RB_UL == 273) {
sampling_frequency = 122.88;
bandwidth = 100;
}
else if (mu == 1 && N_RB_UL == 217) {
sampling_frequency = 122.88;
bandwidth = 80;
}
else if (mu == 1 && N_RB_UL == 106) {
sampling_frequency = 61.44;
bandwidth = 40;
}
else if (mu == 1 && N_RB_UL == 24) {
sampling_frequency = 15.36;
bandwidth = 10;
}
else if (mu == 3 && N_RB_UL == 32) {
sampling_frequency = 61.44;
bandwidth = 50;
}
else {
printf("Add N_RB_UL %d\n",N_RB_UL);
exit(-1);
}
LOG_I( PHY,"++++++++++++++++++++++++++++++++++++++++++++++%i+++++++++++++++++++++++++++++++++++++++++",loglvl);
if (openair0_cfg[0].threequarter_fs == 1) sampling_frequency*=.75;
UE2gNB = new_channel_desc_scm(n_tx, n_rx, channel_model,
......@@ -872,8 +890,12 @@ int main(int argc, char **argv)
/* Additional DMRS positions */
if(dmrs_arg[1] >= 0 && dmrs_arg[1] <=3 )
add_pos = dmrs_arg[1];
/* DMRS Conf Type 1 or 2 */
if(dmrs_arg[2] == 1)
dmrs_config_type = pusch_dmrs_type1;
else if(dmrs_arg[2] == 2)
dmrs_config_type = pusch_dmrs_type2;
}
printf("NOTE: DMRS config is modified with Mapping Type %d , Additional Position %d \n", mapping_type, add_pos );
uint8_t length_dmrs = pusch_len1;
uint16_t l_prime_mask = get_l_prime(nb_symb_sch, mapping_type, add_pos, length_dmrs, start_symbol, NR_MIB__dmrs_TypeA_Position_pos2);
......@@ -892,6 +914,7 @@ int main(int argc, char **argv)
AssertFatal(index >= 0, "Num RBs not configured according to 3GPP 38.211 section 6.3.1.4. For PUSCH with transform precoding, num RBs cannot be multiple of any other primenumber other than 2,3,5\n");
dmrs_config_type = pusch_dmrs_type1;
nb_re_dmrs = 6;
printf("[ULSIM]: TRANSFORM PRECODING ENABLED. Num RBs: %d, index for DMRS_SEQ: %d\n", nb_rb, index);
}
......@@ -1165,6 +1188,7 @@ int main(int argc, char **argv)
ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers;
ul_config.ul_config_list[0].pusch_config_pdu.dmrs_ports = ((1<<precod_nbr_layers)-1);
ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0;
ul_config.ul_config_list[0].pusch_config_pdu.target_code_rate = code_rate;
ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS/8;
ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = trial & 0x1;
......@@ -1559,7 +1583,7 @@ int main(int argc, char **argv)
if(n_trials==1)
break;
if ((float)n_errors[0][snrRun]/(float)n_trials <= target_error_rate) {
if (effRate[snrRun] > (eff_tp_check*TBS)) {
printf("*************\n");
printf("PUSCH test OK\n");
printf("*************\n");
......
......@@ -683,15 +683,15 @@ int DU_handle_UE_CONTEXT_RELEASE_COMMAND(instance_t instance,
"RNTI obtained through DU ID (%x) is different from CU ID (%x)\n",
rnti, ctxt.rnti);
int UE_out_of_sync = 0;
if (RC.nrrrc && RC.nrrrc[instance]->node_type == ngran_gNB_DU) {
for (int n = 0; n < MAX_MOBILES_PER_GNB; ++n) {
if (RC.nrmac[instance]->UE_info.active[n] == TRUE
&& rnti == RC.nrmac[instance]->UE_info.rnti[n]) {
UE_iterator(RC.nrmac[instance]->UE_info.list, UE) {
if (UE->rnti == rnti) {
UE_out_of_sync = 0;
break;
}
}
if (!UE)
LOG_E(F1AP,"Not found rnti: %x\n", rnti);
} else {
for (int n = 0; n < MAX_MOBILES_PER_ENB; ++n) {
if (RC.mac[instance]->UE_info.active[n] == TRUE
......@@ -701,7 +701,6 @@ int DU_handle_UE_CONTEXT_RELEASE_COMMAND(instance_t instance,
}
}
}
/* We don't need the Cause */
/* Optional RRC Container: if present, send to UE */
F1AP_FIND_PROTOCOLIE_BY_ID(F1AP_UEContextReleaseCommandIEs_t, ie, container,
......
......@@ -62,12 +62,15 @@
#define CONFIG_STRING_MACRLC_PUSCHFAILURETHRES "pusch_FailureThres"
#define CONFIG_STRING_MACRLC_DL_BLER_TARGET_UPPER "dl_bler_target_upper"
#define CONFIG_STRING_MACRLC_DL_BLER_TARGET_LOWER "dl_bler_target_lower"
#define CONFIG_STRING_MACRLC_DL_RD2_BLER_THRESHOLD "dl_rd2_bler_threshold"
#define CONFIG_STRING_MACRLC_DL_MAX_MCS "dl_max_mcs"
#define CONFIG_STRING_MACRLC_UL_BLER_TARGET_UPPER "ul_bler_target_upper"
#define CONFIG_STRING_MACRLC_UL_BLER_TARGET_LOWER "ul_bler_target_lower"
#define CONFIG_STRING_MACRLC_UL_MAX_MCS "ul_max_mcs"
#define CONFIG_STRING_MACRLC_HARQ_ROUND_MAX "harq_round_max"
#define CONFIG_STRING_MACRLC_MIN_GRANT_PRB "min_grant_prb"
#define CONFIG_STRING_MACRLC_MIN_GRANT_MCS "min_grant_mcs"
/*-------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* MacRLC configuration parameters */
/* optname helpstr paramflags XXXptr defXXXval type numelt */
......@@ -97,8 +100,10 @@
{CONFIG_STRING_MACRLC_PUSCHFAILURETHRES, NULL, 0, iptr:NULL, defintval:10, TYPE_INT, 0}, \
{CONFIG_STRING_MACRLC_DL_BLER_TARGET_UPPER, "Upper threshold of BLER to decrease DL MCS", 0, dblptr:NULL, defdblval:0.15, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_BLER_TARGET_LOWER, "Lower threshold of BLER to increase DL MCS", 0, dblptr:NULL, defdblval:0.05, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_RD2_BLER_THRESHOLD, "Threshold of RD2/RETX2 BLER to decrease DL MCS", 0, dblptr:NULL, defdblval:0.01, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_MAX_MCS, "Maximum DL MCS that should be used", 0, u8ptr:NULL, defintval:28, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_UL_BLER_TARGET_UPPER, "Upper threshold of BLER to decrease UL MCS", 0, dblptr:NULL, defdblval:0.15, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_UL_BLER_TARGET_LOWER, "Lower threshold of BLER to increase UL MCS", 0, dblptr:NULL, defdblval:0.05, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_UL_MAX_MCS, "Maximum UL MCS that should be used", 0, u8ptr:NULL, defintval:9, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_HARQ_ROUND_MAX, "Maximum number of HARQ rounds", 0, u8ptr:NULL, defintval:4, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_MIN_GRANT_PRB, "Minimal Periodic ULSCH Grant PRBs", 0, u8ptr:NULL, defintval:5, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_MIN_GRANT_MCS, "Minimal Periodic ULSCH Grant MCS", 0, u8ptr:NULL, defintval:9, TYPE_UINT8, 0} \
......@@ -127,10 +132,13 @@
#define MACRLC_PUSCHFAILURETHRES_IDX 21
#define MACRLC_DL_BLER_TARGET_UPPER_IDX 22
#define MACRLC_DL_BLER_TARGET_LOWER_IDX 23
#define MACRLC_DL_RD2_BLER_THRESHOLD_IDX 24
#define MACRLC_DL_MAX_MCS_IDX 25
#define MACRLC_HARQ_ROUND_MAX_IDX 26
#define MACRLC_MIN_GRANT_PRB_IDX 27
#define MACRLC_MIN_GRANT_MCS_IDX 28
#define MACRLC_DL_MAX_MCS_IDX 24
#define MACRLC_UL_BLER_TARGET_UPPER_IDX 25
#define MACRLC_UL_BLER_TARGET_LOWER_IDX 26
#define MACRLC_UL_MAX_MCS_IDX 27
#define MACRLC_HARQ_ROUND_MAX_IDX 28
#define MACRLC_MIN_GRANT_PRB_IDX 29
#define MACRLC_MIN_GRANT_MCS_IDX 30
/*---------------------------------------------------------------------------------------------------------------------------------------------------------*/
#endif
......@@ -213,15 +213,20 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
// *scc->n_TimingAdvanceOffset=NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n0;
*scc->ssb_periodicityServingCell=NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms20;
scc->dmrs_TypeA_Position=NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2;
*scc->ssbSubcarrierSpacing=NR_SubcarrierSpacing_kHz30;
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=641032;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=78;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=640000;
*scc->ssbSubcarrierSpacing=mu_dl;
if (mu_dl == 0) {
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=520432;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=38;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=520000;
} else {
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=641032;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=78;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=640000;
}
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=mu_dl;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_DL;
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth=13036;
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth=275*(N_RB_DL-1);
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing=mu_dl;//NR_SubcarrierSpacing_kHz30;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=12;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero=0;
......@@ -235,13 +240,13 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
timedomainresourceallocation1->startSymbolAndLength=57;
ASN_SEQUENCE_ADD(&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,
timedomainresourceallocation1);
*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]=78;
*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]=mu_ul?78:38;
*scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA=-1;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=mu_ul;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_UL;
*scc->uplinkConfigCommon->frequencyInfoUL->p_Max=20;
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth=13036;
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth=275*(N_RB_UL-1);
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing=mu_ul;//NR_SubcarrierSpacing_kHz30;
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex=98;
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM=NR_RACH_ConfigGeneric__msg1_FDM_one;
......@@ -277,8 +282,11 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
*scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal=-90;
scc->ssb_PositionsInBurst->present=NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap;
*ssb_bitmap=0xff;
scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5;
scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing=mu_dl;
if (mu_dl == 0)
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms10;
else
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots=7;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols=6;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots=2;
......@@ -873,10 +881,14 @@ void RCconfig_nr_macrlc() {
AssertFatal(1==0,"MACRLC %d: %s unknown southbound midhaul\n",j,*(MacRLC_ParamList.paramarray[j][MACRLC_TRANSPORT_S_PREFERENCE_IDX].strptr));
}
RC.nrmac[j]->ulsch_max_frame_inactivity = *(MacRLC_ParamList.paramarray[j][MACRLC_ULSCH_MAX_FRAME_INACTIVITY].uptr);
RC.nrmac[j]->dl_bler_target_upper = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_UPPER_IDX].dblptr);
RC.nrmac[j]->dl_bler_target_lower = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_LOWER_IDX].dblptr);
RC.nrmac[j]->dl_rd2_bler_threshold = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_RD2_BLER_THRESHOLD_IDX].dblptr);
RC.nrmac[j]->dl_max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_MAX_MCS_IDX].u8ptr);
NR_bler_options_t *dl_bler_options = &RC.nrmac[j]->dl_bler;
dl_bler_options->upper = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_UPPER_IDX].dblptr);
dl_bler_options->lower = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_LOWER_IDX].dblptr);
dl_bler_options->max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_MAX_MCS_IDX].u8ptr);
NR_bler_options_t *ul_bler_options = &RC.nrmac[j]->ul_bler;
ul_bler_options->upper = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_BLER_TARGET_UPPER_IDX].dblptr);
ul_bler_options->lower = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_BLER_TARGET_LOWER_IDX].dblptr);
ul_bler_options->max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_MAX_MCS_IDX].u8ptr);
RC.nrmac[j]->harq_round_max = *(MacRLC_ParamList.paramarray[j][MACRLC_HARQ_ROUND_MAX_IDX].u8ptr);
RC.nrmac[j]->min_grant_prb = *(MacRLC_ParamList.paramarray[j][MACRLC_MIN_GRANT_PRB_IDX].u8ptr);
RC.nrmac[j]->min_grant_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_MIN_GRANT_MCS_IDX].u8ptr);
......
......@@ -49,16 +49,15 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t nbp_re, nb_re;
uint32_t nr_tbs=0;
uint32_t Ninfo, Np_info, C;
uint8_t n, scale;
uint8_t n;
LOG_D(NR_MAC, "In %s: nb_symb_sch %d, nb_dmrs_prb %d, nb_rb %d, nb_rb_oh %d, tb_scaling %d Nl %d\n", __FUNCTION__, nb_symb_sch, nb_dmrs_prb, nb_rb, nb_rb_oh, tb_scaling, Nl);
nbp_re = NR_NB_SC_PER_RB * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
nb_re = min(156, nbp_re) * nb_rb;
scale = (R>1024)?11:10;
// Intermediate number of information bits
Ninfo = ((nb_re * R * Qm * Nl)>>scale)>>tb_scaling;
// R is tabulated as 10 times the actual code rate
Ninfo = ((nb_re * R * Qm * Nl / 10)>>10)>>tb_scaling;
if (Ninfo <=3824) {
n = max(3, floor(log2(Ninfo)) - 6);
......@@ -73,7 +72,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
n = log2(Ninfo-24)-5;
Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1<<n)))<<n);
if (R <= 256) {
if (R <= 2560) {
C = CEILIDIV((Np_info+24),3816);
nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24;
} else {
......
......@@ -1686,7 +1686,7 @@ int get_nr_prach_info_from_index(uint8_t index,
}
if ( (s_map>>subframe)&0x01 ) {
*N_RA_slot = table_6_3_3_2_3_prachConfig_Index[index][6]; // Number of RACH slots within a subframe
if (mu == 1) {
if (mu == 1 && index >= 67) {
if ( (*N_RA_slot <= 1) && (slot%2 == 0) )
return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
}
......@@ -2095,17 +2095,15 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS*dmrs_length - N_PRB_oh;
LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh);
uint16_t R;
uint32_t TBS=0;
uint8_t table_idx, Qm;
/*uint8_t mcs_table = config.pdsch_config.mcs_table.value;
uint8_t ss_type = params_rel15.search_space_type;
uint8_t dci_format = params_rel15.dci_format;
get_table_idx(mcs_table, dci_format, rnti_type, ss_type);*/
table_idx = 0;
R = nr_get_code_rate_dl(Imcs, table_idx);
Qm = nr_get_Qm_dl(Imcs, table_idx);
uint8_t table_idx = 0;
uint16_t R = nr_get_code_rate_dl(Imcs, table_idx);
uint8_t Qm = nr_get_Qm_dl(Imcs, table_idx);
TBS = nr_compute_tbs(Qm,
R,
......@@ -2126,25 +2124,25 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords );
}
// the following tables contain 10 times the value reported in 214 (in line with SCF specification and to avoid fractional values)
//Table 5.1.3.1-1 of 38.214
uint16_t Table_51311[29][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616},
{4,658},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}};
uint16_t Table_51311[29][2] = {{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},{4,3400},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},
{4,6580},{6,4380},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720},{6,8220},{6,8730}, {6,9100}, {6,9480}};
//Table 5.1.3.1-2 of 38.214
// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point
uint16_t Table_51312[28][2] = {{2,120},{2,193},{2,308},{2,449},{2,602},{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{6,466},{6,517},{6,567},{6,616},{6,666},
{6,719},{6,772},{6,822},{6,873},{8,1365},{8,711},{8,754},{8,797},{8,841},{8,885},{8,1833},{8,948}};
uint16_t Table_51312[28][2] = {{2,1200},{2,1930},{2,3080},{2,4490},{2,6020},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{4,6580},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},
{6,7190},{6,7720},{6,8220},{6,8730},{8,6825},{8,7110},{8,7540},{8,7970},{8,8410},{8,8850},{8,9165},{8,9480}};
//Table 5.1.3.1-3 of 38.214
uint16_t Table_51313[29][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{4,340},
{4,378},{4,434},{4,490},{4,553},{4,616},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666}, {6,719}, {6,772}};
uint16_t Table_61411[28][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616},
{4,658},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}};
uint16_t Table_51313[29][2] = {{2,300},{2,400},{2,500},{2,640},{2,780},{2,990},{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{4,3400},
{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{6,4380},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720}};
uint16_t Table_61412[28][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},
{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{4,699},{4,772},{6,567},{6,616},{6,666}, {6,772}};
uint16_t Table_61411[28][2] = {{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},{4,3400},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},
{4,6580},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720},{6,8220},{6,8730},{6,9100},{6,9480}};
uint16_t Table_61412[28][2] = {{2,300},{2,400},{2,500},{2,640},{2,780},{2,990},{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},
{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{4,6580},{4,6990},{4,7720},{6,5670},{6,6160},{6,6660},{6,7720}};
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) {
......
......@@ -121,6 +121,23 @@ int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmr
uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table);
uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB);
uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t R,
uint16_t nb_rb,
uint16_t nb_symb_sch,
uint16_t nb_dmrs_prb,
uint16_t nb_rb_oh,
uint8_t tb_scaling,
uint8_t Nl);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for uplink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
uint16_t get_nr_srs_offset(NR_SRS_PeriodicityAndOffset_t periodicityAndOffset);
int get_bw_tbslbrm(NR_BWP_t *genericParameters,
......
......@@ -936,6 +936,23 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
return -1;
}
dlsch_config_pdu_1_0->qamModOrder = nr_get_Qm_dl(dlsch_config_pdu_1_0->mcs, dlsch_config_pdu_1_0->mcs_table);
int R = nr_get_code_rate_dl(dlsch_config_pdu_1_0->mcs, dlsch_config_pdu_1_0->mcs_table);
dlsch_config_pdu_1_0->targetCodeRate = R;
if (dlsch_config_pdu_1_0->targetCodeRate == 0 || dlsch_config_pdu_1_0->qamModOrder == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dlsch_config_pdu_1_0->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) ? 6:4)*dlsch_config_pdu_1_0->n_dmrs_cdm_groups;
dlsch_config_pdu_1_0->TBS = nr_compute_tbs(dlsch_config_pdu_1_0->qamModOrder,
R,
dlsch_config_pdu_1_0->number_rbs,
dlsch_config_pdu_1_0->number_symbols,
nb_re_dmrs*get_num_dmrs(dlsch_config_pdu_1_0->dlDmrsSymbPos),
nb_rb_oh, 0, 1);
int bw_tbslbrm;
if (mac->scc || mac->scc_SIB || mac->cg) {
NR_BWP_t genericParameters = mac->scc ? mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters :
......@@ -1353,6 +1370,25 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
dl_config->number_pdus = dl_config->number_pdus + 1;
/* TODO same calculation for MCS table as done in UL */
dlsch_config_pdu_1_1->mcs_table = (pdsch_Config->mcs_Table) ? (*pdsch_Config->mcs_Table + 1) : 0;
dlsch_config_pdu_1_1->qamModOrder = nr_get_Qm_dl(dlsch_config_pdu_1_1->mcs, dlsch_config_pdu_1_1->mcs_table);
int R = nr_get_code_rate_dl(dlsch_config_pdu_1_1->mcs, dlsch_config_pdu_1_1->mcs_table);
dlsch_config_pdu_1_1->targetCodeRate = R;
if (dlsch_config_pdu_1_1->targetCodeRate == 0 || dlsch_config_pdu_1_1->qamModOrder == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
uint8_t Nl = 0;
for (int i = 0; i < 12; i++) { // max 12 ports
if ((dlsch_config_pdu_1_1->dmrs_ports>>i)&0x01) Nl += 1;
}
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dmrs_type == NULL) ? 6:4)*dlsch_config_pdu_1_1->n_dmrs_cdm_groups;
dlsch_config_pdu_1_1->TBS = nr_compute_tbs(dlsch_config_pdu_1_1->qamModOrder,
R,
dlsch_config_pdu_1_1->number_rbs,
dlsch_config_pdu_1_1->number_symbols,
nb_re_dmrs*get_num_dmrs(dlsch_config_pdu_1_1->dlDmrsSymbPos),
nb_rb_oh, 0, Nl);
// TBS_LBRM according to section 5.4.2.1 of 38.212
long *maxMIMO_Layers = mac->cg->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers;
......
......@@ -840,12 +840,14 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
mappingtype, add_pos, dmrslength,
pusch_config_pdu->start_symbol_index,
mac->scc ? mac->scc->dmrs_TypeA_Position : mac->mib->dmrs_TypeA_Position);
if ((mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_disabled))
if ((mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_disabled)) {
if (*dci_format != NR_UL_DCI_FORMAT_0_1) {
pusch_config_pdu->num_dmrs_cdm_grps_no_data = 1;
}
else if (*dci_format == NR_UL_DCI_FORMAT_0_0 || (mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_enabled))
} else if (*dci_format == NR_UL_DCI_FORMAT_0_0 ||
(mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_enabled)) {
pusch_config_pdu->num_dmrs_cdm_grps_no_data = 2;
}
// Num PRB Overhead from PUSCH-ServingCellConfig
if (mac->cg &&
......@@ -891,7 +893,8 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
rnti_types[rnti_type]);
pusch_config_pdu->ul_dmrs_symb_pos = l_prime_mask;
pusch_config_pdu->target_code_rate = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
uint16_t R = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
pusch_config_pdu->target_code_rate = R;
pusch_config_pdu->qam_mod_order = nr_get_Qm_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
if (pusch_config_pdu->target_code_rate == 0 || pusch_config_pdu->qam_mod_order == 0) {
......@@ -910,14 +913,13 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
// Compute TBS
pusch_config_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_config_pdu->qam_mod_order,
pusch_config_pdu->target_code_rate,
R,
pusch_config_pdu->rb_size,
pusch_config_pdu->nr_of_symbols,
nb_dmrs_re_per_rb*number_dmrs_symbols,
N_PRB_oh,
0, // TBR to verify tb scaling
pusch_config_pdu->nrOfLayers)/8;
pusch_config_pdu->nrOfLayers)>>3;
return 0;
}
......@@ -1087,7 +1089,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
fill_scheduled_response(&scheduled_response, &dcireq.dl_config_req, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id, dl_info->phy_data);
if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL)
LOG_D(NR_MAC,"1# scheduled_response transmitted, %d, %d\n", rx_frame, rx_slot);
mac->if_module->scheduled_response(&scheduled_response);
mac->if_module->scheduled_response(&scheduled_response);
}
else {
// this is for Msg2/Msg4
......
......@@ -455,18 +455,17 @@ int nr_mac_enable_ue_rrc_processing_timer(module_id_t Mod_idP, rnti_t rnti, NR_S
if (rrc_reconfiguration_delay == 0) {
return -1;
}
const int UE_id = find_nr_UE_id(Mod_idP,rnti);
if (UE_id < 0) {
NR_UE_info_t *UE_info = find_nr_UE(&RC.nrmac[Mod_idP]->UE_info,rnti);
if (!UE_info) {
LOG_W(NR_MAC, "Could not find UE for RNTI 0x%04x\n", rnti);
return -1;
}
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl;
const uint16_t sf_ahead = 6/(0x01<<subcarrierSpacing) + ((6%(0x01<<subcarrierSpacing))>0);
const uint16_t sl_ahead = sf_ahead * (0x01<<subcarrierSpacing);
sched_ctrl->rrc_processing_timer = (rrc_reconfiguration_delay<<subcarrierSpacing) + sl_ahead;
LOG_I(NR_MAC, "Activating RRC processing timer for UE %d with %d ms\n", UE_id, rrc_reconfiguration_delay);
LOG_I(NR_MAC, "Activating RRC processing timer for UE %04x with %d ms\n", UE_info->rnti, rrc_reconfiguration_delay);
return 0;
}
......@@ -551,9 +550,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
AssertFatal(RC.nrmac[Mod_idP]->common_channels[0].frame_type == FDD,"Dynamic TDD not handled yet\n");
for (int slot = 0; slot < n; ++slot) {
if (RC.nrmac[Mod_idP]->common_channels[0].frame_type == FDD ||
(slot != 0))
RC.nrmac[Mod_idP]->dlsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) < nr_dl_slots) << (slot % 64);
RC.nrmac[Mod_idP]->dlsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) < nr_dl_slots) << (slot % 64);
RC.nrmac[Mod_idP]->ulsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) >= nr_ulstart_slot) << (slot % 64);
LOG_I(NR_MAC, "In %s: slot %d DL %d UL %d\n",
......@@ -591,37 +588,19 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (CellGroup) {
if (get_softmodem_params()->sa) {
calculate_preferred_dl_tda(Mod_idP, NULL);
}
const NR_ServingCellConfig_t *servingCellConfig = NULL;
if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated) {
if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
servingCellConfig = CellGroup->spCellConfig->spCellConfigDedicated;
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
if(bwpList) {
AssertFatal(bwpList->list.count > 0, "downlinkBWP_ToAddModList has no BWPs!\n");
for (int i = 0; i < bwpList->list.count; ++i) {
const NR_BWP_Downlink_t *bwp = bwpList->list.array[i];
calculate_preferred_dl_tda(Mod_idP, bwp);
}
}
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
if(ubwpList) {
AssertFatal(ubwpList->list.count > 0, "uplinkBWP_ToAddModList no BWPs!\n");
for (int i = 0; i < ubwpList->list.count; ++i) {
const NR_BWP_Uplink_t *ubwp = ubwpList->list.array[i];
calculate_preferred_ul_tda(Mod_idP, ubwp);
}
}
}
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
if (add_ue == 1 && get_softmodem_params()->phy_test) {
const int UE_id = add_new_nr_ue(Mod_idP, rnti, CellGroup);
LOG_I(NR_MAC,"Added new UE_id %d/%x with initial CellGroup\n",UE_id,rnti);
process_CellGroup(CellGroup,&UE_info->UE_sched_ctrl[UE_id]);
NR_UE_info_t* UE = add_new_nr_ue(RC.nrmac[Mod_idP], rnti, CellGroup);
if (UE)
LOG_I(NR_MAC,"Added new UE %x with initial CellGroup\n", rnti);
else {
LOG_E(NR_MAC,"Error adding UE %04x\n", rnti);
return -1;
}
process_CellGroup(CellGroup,&UE->UE_sched_ctrl);
} else if (add_ue == 1 && !get_softmodem_params()->phy_test) {
const int CC_id = 0;
NR_COMMON_channels_t *cc = &RC.nrmac[Mod_idP]->common_channels[CC_id];
......@@ -668,12 +647,18 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
LOG_I(NR_MAC,"Added new RA process for UE RNTI %04x with initial CellGroup\n", rnti);
} else { // CellGroup has been updated
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels[0].ServingCellConfigCommon;
const int UE_id = find_nr_UE_id(Mod_idP,rnti);
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[Mod_idP]->UE_info,rnti);
if (!UE) {
LOG_E(NR_MAC, "Can't find UE %04x\n", rnti);
return -1;
}
int target_ss;
UE_info->CellGroup[UE_id] = CellGroup;
LOG_I(NR_MAC,"Modified UE_id %d/%x with CellGroup\n",UE_id,rnti);
process_CellGroup(CellGroup,&UE_info->UE_sched_ctrl[UE_id]);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE->CellGroup = CellGroup;
LOG_I(NR_MAC,"Modified rnti %04x with CellGroup\n",rnti);
process_CellGroup(CellGroup,&UE->UE_sched_ctrl);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const NR_PDSCH_ServingCellConfig_t *pdsch = servingCellConfig ? servingCellConfig->pdsch_ServingCellConfig->choice.setup : NULL;
if (get_softmodem_params()->sa) {
// add all available DL HARQ processes for this UE in SA
......@@ -696,7 +681,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
}
sched_ctrl->search_space = get_searchspace(sib1 ? sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL, scc, bwpd, target_ss);
sched_ctrl->coreset = get_coreset(Mod_idP, scc, bwpd, sched_ctrl->search_space, target_ss);
sched_ctrl->coreset = get_coreset(RC.nrmac[Mod_idP], scc, bwpd, sched_ctrl->search_space, target_ss);
sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP],
sched_ctrl->search_space,
sched_ctrl->coreset,
......@@ -709,7 +694,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig &&
CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup
)
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE_info, UE_id, Mod_idP);
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE);
}
}
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT);
......
......@@ -104,167 +104,6 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
TX_req[CC_idP].Number_of_PDUs = 0;
}
/*
void check_nr_ul_failure(module_id_t module_idP,
int CC_id,
int UE_id,
frame_t frameP,
sub_frame_t slotP) {
NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
nfapi_nr_dl_dci_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0];
uint16_t rnti = UE_RNTI(module_idP, UE_id);
NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels;
// check uplink failure
if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0) &&
(UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 0)) {
LOG_I(MAC, "UE %d rnti %x: UL Failure timer %d \n", UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer);
if (UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent == 0) {
UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1;
// add a format 1A dci for this UE to request an RA procedure (only one UE per subframe)
nfapi_nr_dl_dci_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_tti_request_body.dl_config_pdu_list[DL_req[CC_id].dl_tti_request_body.number_pdu];
memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_dci_request_pdu_t));
dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE;
dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu));
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_DCI_REQUEST_DCI_DL_PDU_REL8_TAG;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP, CC_id),
UE_info->UE_sched_ctrl[UE_id].
dl_cqi[CC_id], format1A);
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power
AssertFatal((cc[CC_id].mib->message.dl_Bandwidth >= 0) && (cc[CC_id].mib->message.dl_Bandwidth < 6),
"illegal dl_Bandwidth %d\n",
(int) cc[CC_id].mib->message.dl_Bandwidth);
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = nr_pdcch_order_table[cc[CC_id].mib->message.dl_Bandwidth];
DL_req[CC_id].dl_tti_request_body.number_dci++;
DL_req[CC_id].dl_tti_request_body.number_pdu++;
DL_req[CC_id].dl_tti_request_body.tl.tag = NFAPI_DL_TTI_REQUEST_BODY_TAG;
LOG_I(MAC,
"UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d), resource_block_coding %d \n",
UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer,
dl_config_pdu->dci_dl_pdu.
dci_dl_pdu_rel8.resource_block_coding);
} else { // ra_pdcch_sent==1
LOG_I(MAC,
"UE %d rnti %x: sent PDCCH order for RAPROC waiting (failure timer %d) \n",
UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer);
if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer % 40) == 0) UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 4 frames
}
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer++;
// check threshold
if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 20000) {
// inform RRC of failure and clear timer
LOG_I(MAC,
"UE %d rnti %x: UL Failure after repeated PDCCH orders: Triggering RRC \n",
UE_id, rnti);
mac_eNB_rrc_ul_failure(module_idP, CC_id, frameP, subframeP,rnti);
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync = 1;
//Inform the controller about the UE deactivation. Should be moved to RRC agent in the future
if (rrc_agent_registered[module_idP]) {
LOG_W(MAC, "notify flexran Agent of UE state change\n");
agent_rrc_xface[module_idP]->flexran_agent_notify_ue_state_change(module_idP,
rnti, PROTOCOL__FLEX_UE_STATE_CHANGE_TYPE__FLUESC_DEACTIVATED);
}
}
} // ul_failure_timer>0
}
*/
/*
void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP)
{
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_UE_info_t *UE_info = &gNB->UE_info;
nfapi_ul_config_request_body_t *ul_req;
int CC_id, UE_id;
NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels;
SoundingRS_UL_ConfigCommon_t *soundingRS_UL_ConfigCommon;
struct SoundingRS_UL_ConfigDedicated *soundingRS_UL_ConfigDedicated;
uint8_t TSFC;
uint16_t deltaTSFC; // bitmap
uint8_t srs_SubframeConfig;
// table for TSFC (Period) and deltaSFC (offset)
const uint16_t deltaTSFCTabType1[15][2] = { {1, 1}, {1, 2}, {2, 2}, {1, 5}, {2, 5}, {4, 5}, {8, 5}, {3, 5}, {12, 5}, {1, 10}, {2, 10}, {4, 10}, {8, 10}, {351, 10}, {383, 10} }; // Table 5.5.3.3-2 3GPP 36.211 FDD
const uint16_t deltaTSFCTabType2[14][2] = { {2, 5}, {6, 5}, {10, 5}, {18, 5}, {14, 5}, {22, 5}, {26, 5}, {30, 5}, {70, 10}, {74, 10}, {194, 10}, {326, 10}, {586, 10}, {210, 10} }; // Table 5.5.3.3-2 3GPP 36.211 TDD
uint16_t srsPeriodicity, srsOffset;
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
soundingRS_UL_ConfigCommon = &cc[CC_id].radioResourceConfigCommon->soundingRS_UL_ConfigCommon;
// check if SRS is enabled in this frame/subframe
if (soundingRS_UL_ConfigCommon) {
srs_SubframeConfig = soundingRS_UL_ConfigCommon->choice.setup.srs_SubframeConfig;
if (cc[CC_id].tdd_Config == NULL) { // FDD
deltaTSFC = deltaTSFCTabType1[srs_SubframeConfig][0];
TSFC = deltaTSFCTabType1[srs_SubframeConfig][1];
} else { // TDD
deltaTSFC = deltaTSFCTabType2[srs_SubframeConfig][0];
TSFC = deltaTSFCTabType2[srs_SubframeConfig][1];
}
// Sounding reference signal subframes are the subframes satisfying ns/2 mod TSFC (- deltaTSFC
uint16_t tmp = (subframeP % TSFC);
if ((1 << tmp) & deltaTSFC) {
// This is an SRS subframe, loop over UEs
for (UE_id = 0; UE_id < MAX_MOBILES_PER_GNB; UE_id++) {
if (!RC.nrmac[module_idP]->UE_info.active[UE_id]) continue;
ul_req = &RC.nrmac[module_idP]->UL_req[CC_id].ul_config_request_body;
// drop the allocation if the UE hasn't send RRCConnectionSetupComplete yet
if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED) continue;
AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated != NULL,
"physicalConfigDedicated is null for UE %d\n",
UE_id);
if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated) != NULL) {
if (soundingRS_UL_ConfigDedicated->present == SoundingRS_UL_ConfigDedicated_PR_setup) {
get_srs_pos(&cc[CC_id],
soundingRS_UL_ConfigDedicated->choice.
setup.srs_ConfigIndex,
&srsPeriodicity, &srsOffset);
if (((10 * frameP + subframeP) % srsPeriodicity) == srsOffset) {
// Program SRS
ul_req->srs_present = 1;
nfapi_ul_config_request_pdu_t * ul_config_pdu = &ul_req->ul_config_pdu_list[ul_req->number_of_pdus];
memset((void *) ul_config_pdu, 0, sizeof(nfapi_ul_config_request_pdu_t));
ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_SRS_PDU_TYPE;
ul_config_pdu->pdu_size = 2 + (uint8_t) (2 + sizeof(nfapi_ul_config_srs_pdu));
ul_config_pdu->srs_pdu.srs_pdu_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_SRS_PDU_REL8_TAG;
ul_config_pdu->srs_pdu.srs_pdu_rel8.size = (uint8_t)sizeof(nfapi_ul_config_srs_pdu);
ul_config_pdu->srs_pdu.srs_pdu_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti;
ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_Bandwidth;
ul_config_pdu->srs_pdu.srs_pdu_rel8.frequency_domain_position = soundingRS_UL_ConfigDedicated->choice.setup.freqDomainPosition;
ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_hopping_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_HoppingBandwidth;;
ul_config_pdu->srs_pdu.srs_pdu_rel8.transmission_comb = soundingRS_UL_ConfigDedicated->choice.setup.transmissionComb;
ul_config_pdu->srs_pdu.srs_pdu_rel8.i_srs = soundingRS_UL_ConfigDedicated->choice.setup.srs_ConfigIndex;
ul_config_pdu->srs_pdu.srs_pdu_rel8.sounding_reference_cyclic_shift = soundingRS_UL_ConfigDedicated->choice.setup.cyclicShift; // ul_config_pdu->srs_pdu.srs_pdu_rel10.antenna_port = ;//
// ul_config_pdu->srs_pdu.srs_pdu_rel13.number_of_combs = ;//
RC.nrmac[module_idP]->UL_req[CC_id].sfn_sf = (frameP << 4) + subframeP;
RC.nrmac[module_idP]->UL_req[CC_id].header.message_id = NFAPI_UL_CONFIG_REQUEST;
ul_req->number_of_pdus++;
} // if (((10*frameP+subframeP) % srsPeriodicity) == srsOffset)
} // if (soundingRS_UL_ConfigDedicated->present == SoundingRS_UL_ConfigDedicated_PR_setup)
} // if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated)!=NULL)
} // for (UE_id ...
} // if((1<<tmp) & deltaTSFC)
} // SRS config
}
}
*/
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) {
if (slot>=64) return false; //quickfix for FR2 where there are more than 64 slots (bitmap to be removed)
......@@ -372,7 +211,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
schedule_nr_prach(module_idP, f, s);
}
// Schedule CSI-RS transmission
nr_csirs_scheduling(module_idP, frame, slot, nr_slots_per_frame[*scc->ssbSubcarrierSpacing]);
......@@ -398,10 +236,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_schedule_ue_spec(module_idP, frame, slot);
stop_meas(&gNB->schedule_dlsch);
nr_schedule_pucch(module_idP, frame, slot);
nr_schedule_pucch(RC.nrmac[module_idP], frame, slot);
// This schedule SR after PUCCH for multiplexing
nr_sr_reporting(module_idP, frame, slot);
nr_sr_reporting(RC.nrmac[module_idP], frame, slot);
stop_meas(&RC.nrmac[module_idP]->eNB_scheduler);
......
......@@ -465,27 +465,24 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
int FR = *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0] >= 257 ? nr_FR2 : nr_FR1;
uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
uint8_t start_next_period = rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot;
int eff_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
// we can't schedule msg2 before sl_ahead since prach
int eff_slot = *msg2_slot+(*msg2_frame-rach_frame)*nr_slots_per_frame[mu];
while ((eff_slot-rach_slot)<=sl_ahead) {
*msg2_slot = (*msg2_slot+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
eff_slot = *msg2_slot+(*msg2_frame-rach_frame)*nr_slots_per_frame[mu];
eff_slot += tdd_period_slot;
}
if (FR==nr_FR2) {
int num_tdd_period = *msg2_slot/tdd_period_slot;
int num_tdd_period = (eff_slot%nr_slots_per_frame[mu])/tdd_period_slot;
while((tdd_beam_association[num_tdd_period]!=-1)&&(tdd_beam_association[num_tdd_period]!=beam_index)) {
*msg2_slot = (*msg2_slot+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
num_tdd_period = *msg2_slot/tdd_period_slot;
eff_slot += tdd_period_slot;
num_tdd_period = (eff_slot % nr_slots_per_frame[mu])/tdd_period_slot;
}
if(tdd_beam_association[num_tdd_period] == -1)
tdd_beam_association[num_tdd_period] = beam_index;
}
*msg2_frame=(rach_frame + eff_slot/nr_slots_per_frame[mu])%1024;
*msg2_slot=eff_slot%nr_slots_per_frame[mu];
// go to previous slot if the current scheduled slot is beyond the response window
// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
while (*msg2_frame > frame_limit
......@@ -542,8 +539,10 @@ void nr_initiate_ra_proc(module_id_t module_idP,
for (int i = 0; i < NR_NB_RA_PROC_MAX; i++) {
NR_RA_t *ra = &cc->ra[i];
pr_found = 0;
const int UE_id = find_nr_UE_id(module_idP, ra->rnti);
if (UE_id != -1) {
const NR_UE_info_t * UE = find_nr_UE(&nr_mac->UE_info, ra->rnti);
if (UE) {
// the UE is already registered
LOG_W(NR_MAC, "Received RA for existing RNTI %04x\n", ra->rnti);
continue;
}
if (ra->state == RA_IDLE) {
......@@ -637,7 +636,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
AssertFatal(ra->ra_ss!=NULL,"SearchSpace cannot be null for RA\n");
ra->coreset = get_coreset(module_idP, scc, bwp, ra->ra_ss, NR_SearchSpace__searchSpaceType_PR_common);
ra->coreset = get_coreset(nr_mac, scc, bwp, ra->ra_ss, NR_SearchSpace__searchSpaceType_PR_common);
ra->sched_pdcch = set_pdcch_structure(nr_mac,
ra->ra_ss,
ra->coreset,
......@@ -672,7 +671,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->rnti = (taus() % 65518) + 1;
loop++;
} while (loop != 100
&& !((find_nr_UE_id(module_idP, ra->rnti) == -1) && (find_nr_RA_id(module_idP, CC_id, ra->rnti) == -1)
&& !((find_nr_UE(&nr_mac->UE_info, ra->rnti) == NULL) && (find_nr_RA_id(module_idP, CC_id, ra->rnti) == -1)
&& ra->rnti >= 1 && ra->rnti <= 65519));
if (loop == 100) {
LOG_E(NR_MAC, "%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__);
......@@ -685,7 +684,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->beam_id = beam_index;
LOG_I(NR_MAC,
"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x SSB "
"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x SSB, new rnti %04x "
"index %u RA index %d\n",
module_idP,
CC_id,
......@@ -693,6 +692,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->Msg2_frame,
ra->Msg2_slot,
ra->RA_rnti,
ra->rnti,
cc->ssb_index[beam_index],
i);
......@@ -1109,10 +1109,11 @@ void fill_msg3_pusch_pdu(nfapi_nr_pusch_pdu_t *pusch_pdu,
int TBS = 0;
while(TBS<7) { // TBS for msg3 is 7 bytes (except for RRCResumeRequest1 currently not implemented)
mcsindex++;
pusch_pdu->target_code_rate = nr_get_code_rate_ul(mcsindex,pusch_pdu->mcs_table);
int R = nr_get_code_rate_ul(mcsindex,pusch_pdu->mcs_table);
pusch_pdu->target_code_rate = R;
pusch_pdu->qam_mod_order = nr_get_Qm_ul(mcsindex,pusch_pdu->mcs_table);
TBS = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
R,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
num_dmrs_symb*12, // nb dmrs set for no data in dmrs symbol
......@@ -1200,20 +1201,13 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t
nr_fill_rar(module_idP, ra, RAR_pdu, pusch_pdu);
}
void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t *ra)
{
void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t *ra) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
//TODO time domain assignment for msg2 needs to be improved
uint8_t time_domain_assignment;
if(cc->frame_type == TDD)
time_domain_assignment = 1;
else
time_domain_assignment = 0;
int mcsIndex = -1; // initialization value
int rbStart = 0;
int rbSize = 8;
......@@ -1253,6 +1247,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
}
// Calculate number of symbols
int time_domain_assignment = get_dl_tda(nr_mac, scc, slotP);
int startSymbolIndex, nrOfSymbols;
const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
......@@ -1525,7 +1520,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
}
ra->state = WAIT_Msg3;
LOG_D(NR_MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
LOG_W(NR_MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: rnti %04x RA state %d\n", module_idP, frameP, slotP, ra->rnti, ra->state);
}
}
......@@ -1568,9 +1563,14 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
ra->rnti = ra->crnti;
}
int UE_id = find_nr_UE_id(module_idP, ra->rnti);
NR_UE_info_t *UE_info = &nr_mac->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_info_t * UE = find_nr_UE(&nr_mac->UE_info, ra->rnti);
if (!UE) {
LOG_E(NR_MAC,"want to generate Msg4, but rnti %04x not in the table\n", ra->rnti);
return;
}
LOG_I(NR_MAC,"Generate msg4, rnti: %04x\n", ra->rnti);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_BWP_t *genericParameters = bwp ? & bwp->bwp_Common->genericParameters : &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
......@@ -1603,7 +1603,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// Remove UE associated to TC-RNTI
if(harq->round==0 && ra->msg3_dcch_dtch) {
mac_remove_nr_ue(module_idP, tc_rnti);
mac_remove_nr_ue(nr_mac, tc_rnti);
}
// get CCEindex, needed also for PUCCH and then later for PDCCH
......@@ -1634,7 +1634,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
LOG_D(NR_MAC,"[RAPROC] Msg4 r_pucch %d (CCEIndex %d, nb_of_candidates %d, delta_PRI %d)\n", r_pucch, CCEIndex, nr_of_candidates, delta_PRI);
int alloc = nr_acknack_scheduling(module_idP, UE_id, frameP, slotP, r_pucch, 1);
int alloc = nr_acknack_scheduling(module_idP, UE, frameP, slotP, r_pucch, 1);
AssertFatal(alloc>=0,"Couldn't find a pucch allocation for ack nack (msg4)\n");
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[alloc];
harq->feedback_slot = pucch->ul_slot;
......@@ -1799,7 +1799,8 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15->SubcarrierSpacing = genericParameters->subcarrierSpacing;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,mcsTableIdx);
int R = nr_get_code_rate_dl(mcsIndex,mcsTableIdx);
pdsch_pdu_rel15->targetCodeRate[0] = R;
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx;
......@@ -1949,10 +1950,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if(ra->msg3_dcch_dtch) {
// If the UE used MSG3 to transfer a DCCH or DTCH message, then contention resolution is successful upon transmission of PDCCH
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) CBRA procedure succeeded!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(ue rnti 0x%04x) CBRA procedure succeeded!\n", ra->rnti);
nr_clear_ra_proc(module_idP, CC_id, frameP, ra);
UE_info->active[UE_id] = true;
UE_info->Msg4_ACKed[UE_id] = true;
UE->Msg4_ACKed = true;
remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
harq->feedback_slot = -1;
......@@ -1969,28 +1969,27 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_frame_t slot, NR_RA_t *ra) {
int UE_id = find_nr_UE_id(module_id, ra->rnti);
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[module_id]->UE_info, ra->rnti);
const int current_harq_pid = ra->harq_pid;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
NR_mac_stats_t *stats = &UE_info->mac_stats[UE_id];
NR_mac_stats_t *stats = &UE->mac_stats;
LOG_D(NR_MAC, "ue %d, rnti 0x%04x, harq is waiting %d, round %d, frame %d %d, harq id %d\n", UE_id, ra->rnti, harq->is_waiting, harq->round, frame, slot, current_harq_pid);
LOG_D(NR_MAC, "ue rnti 0x%04x, harq is waiting %d, round %d, frame %d %d, harq id %d\n", ra->rnti, harq->is_waiting, harq->round, frame, slot, current_harq_pid);
if (harq->is_waiting == 0) {
if (harq->round == 0) {
if (stats->dlsch_errors == 0) {
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) Received Ack of RA-Msg4. CBRA procedure succeeded!\n", UE_id, ra->rnti);
UE_info->active[UE_id] = true;
UE_info->Msg4_ACKed[UE_id] = true;
if (stats->dl.errors == 0) {
LOG_A(NR_MAC, "(UE RNTI 0x%04x) Received Ack of RA-Msg4. CBRA procedure succeeded!\n", ra->rnti);
UE->Msg4_ACKed = true;
// Pause scheduling according to:
// 3GPP TS 38.331 Section 12 Table 12.1-1: UE performance requirements for RRC procedures for UEs
const NR_COMMON_channels_t *common_channels = &RC.nrmac[module_id]->common_channels[0];
const NR_SIB1_t *sib1 = common_channels->sib1 ? common_channels->sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
const NR_ServingCellConfig_t *servingCellConfig = UE_info->CellGroup[UE_id] ? UE_info->CellGroup[UE_id]->spCellConfig->spCellConfigDedicated : NULL;
const NR_ServingCellConfig_t *servingCellConfig = UE->CellGroup ? UE->CellGroup->spCellConfig->spCellConfigDedicated : NULL;
NR_BWP_t *genericParameters = get_dl_bwp_genericParameters(sched_ctrl->active_bwp,
common_channels->ServingCellConfigCommon,
sib1);
......@@ -1998,9 +1997,9 @@ void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_fram
NR_RRC_SETUP_DELAY_MS + NR_RRC_BWP_SWITCHING_DELAY_MS : NR_RRC_SETUP_DELAY_MS;
sched_ctrl->rrc_processing_timer = (delay_ms << genericParameters->subcarrierSpacing);
LOG_I(NR_MAC, "(%d.%d) Activating RRC processing timer for UE %d with %d ms\n", frame, slot, UE_id, delay_ms);
LOG_I(NR_MAC, "(%d.%d) Activating RRC processing timer for UE %04x with %d ms\n", frame, slot, UE->rnti, delay_ms);
} else {
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) RA Procedure failed at Msg4!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(ue rnti 0x%04x) RA Procedure failed at Msg4!\n", ra->rnti);
}
nr_clear_ra_proc(module_id, CC_id, frame, ra);
......@@ -2008,7 +2007,7 @@ void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_fram
remove_nr_list(&sched_ctrl->retrans_dl_harq, current_harq_pid);
}
} else {
LOG_D(NR_MAC, "(ue %i, rnti 0x%04x) Received Nack of RA-Msg4. Preparing retransmission!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(UE %04x) Received Nack of RA-Msg4. Preparing retransmission!\n", ra->rnti);
ra->Msg4_frame = (frame + 1) % 1024;
ra->Msg4_slot = 1;
ra->state = Msg4;
......
......@@ -69,7 +69,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
nfapi_nr_pdu_t *TX_req;
uint16_t rnti = 0x1234;
// int time_domain_assignment,k0;
NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon;
......@@ -152,8 +151,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
NrOfSymbols = NrOfSymbols_tmp;
StartSymbolIndex = StartSymbolIndex_tmp;
mappingtype = mappingtype_tmp;
// k0 = *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0;
// time_domain_assignment = i;
}
}
AssertFatal(StartSymbolIndex>=0,"StartSymbolIndex is negative\n");
......@@ -165,78 +162,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
StartSymbolIndex,
mappingtype, 1);
/*
AssertFatal(k0==0,"k0 is not zero for Initial DL BWP TimeDomain Alloc\n");
nr_configure_css_dci_initial(pdcch_pdu_rel15,
scs,
scs,
FR,
0,
0,
0,
sfn_sf, slotP,
slots_per_frame,
dlBWP_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
dlBWP_carrier_bandwidth);
pdu_rel15->time_domain_assignment = time_domain_assignment;
pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 9;
pdu_rel15->tb_scaling = 1;
pdu_rel15->ra_preamble_index = 25;
pdu_rel15->format_indicator = 1;
pdu_rel15->ndi = 1;
pdu_rel15->rv = 0;
pdu_rel15->harq_pid = 0;
pdu_rel15->dai = 2;
pdu_rel15->tpc = 2;
pdu_rel15->pucch_resource_indicator = 7;
pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
pdu_rel15->frequency_domain_assignment,
pdu_rel15->time_domain_assignment,
pdu_rel15->vrb_to_prb_mapping,
pdu_rel15->mcs,
pdu_rel15->tb_scaling,
pdu_rel15->ndi,
pdu_rel15->rv);
params_rel15->rnti = rnti;
params_rel15->rnti_type = NFAPI_NR_RNTI_C;
params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0;
//params_rel15->aggregation_level = 1;
LOG_D(MAC, "DCI type 1 params: rnti %x, rnti_type %d, dci_format %d\n \
coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \
ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d\n",
params_rel15->rnti,
params_rel15->rnti_type,
params_rel15->dci_format,
params_rel15->mux_pattern,
params_rel15->n_rb,
params_rel15->n_symb,
params_rel15->rb_offset,
params_rel15->nb_ss_sets_per_slot,
params_rel15->first_symbol,
params_rel15->nb_slots,
params_rel15->sfn_mod2,
params_rel15->first_slot);
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, dl_tti_dci_pdu->dci_dl_pdu,0);
LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d\n",
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->StartSymbolIndex,
pdsch_pdu_rel15->NrOfSymbols,
pdsch_pdu_rel15->nrOfLayers,
pdsch_pdu_rel15->NrOfCodewords,
pdsch_pdu_rel15->mcsIndex[0]);
*/
nr_mac->DL_req[CC_id].dl_tti_request_body.nPDUs+=2;
TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
......@@ -266,20 +191,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
{
if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot))
return;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0];
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
const int UE_id = 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int CC_id = 0;
AssertFatal(UE_info->active[UE_id],
"%s(): expected UE %d to be active\n",
__func__,
UE_id);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
ps->nrOfLayers = target_dl_Nl;
if (ps->time_domain_allocation != tda || ps->nrOfLayers != target_dl_Nl)
nr_set_pdsch_semi_static(NULL, scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, NULL, tda, target_dl_Nl, sched_ctrl, ps);
nr_set_pdsch_semi_static(NULL, scc, UE->CellGroup, sched_ctrl->active_bwp, NULL, tda, target_dl_Nl,sched_ctrl , ps);
/* find largest unallocated chunk */
const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
......@@ -315,7 +236,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
sched_ctrl->dl_lc_num = 1;
const int lcid = DL_SCH_LCID_DTCH;
sched_ctrl->dl_lc_ids[sched_ctrl->dl_lc_num - 1] = lcid;
const uint16_t rnti = UE_info->rnti[UE_id];
const uint16_t rnti = UE->rnti;
/* update sched_ctrl->num_total_bytes so that postprocessor schedules data,
* if available */
sched_ctrl->rlc_status[lcid] = mac_rlc_status_ind(module_id,
......@@ -342,7 +263,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, UE->rnti);
int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
CC_id,
......@@ -353,17 +274,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
Y);
AssertFatal(CCEIndex >= 0,
"%s(): could not find CCE for UE %d\n",
"%s(): could not find CCE for UE %04x\n",
__func__,
UE_id);
UE->rnti);
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, sched_ctrl->active_ubwp, NULL, CCEIndex);
const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot, r_pucch, 0);
const int alloc = nr_acknack_scheduling(module_id, UE, frame, slot, r_pucch, 0);
if (alloc < 0) {
LOG_D(MAC,
"%s(): could not find PUCCH for UE %d/%04x@%d.%d\n",
"%s(): could not find PUCCH for UE %04x@%d.%d\n",
__func__,
UE_id,
rnti,
frame,
slot);
......@@ -421,32 +341,36 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
NR_UE_info_t *UE_info = &nr_mac->UE_info;
NR_UE_info_t *UE = nr_mac->UE_info.list[0];
AssertFatal(UE_info->num_UEs <= 1,
"%s() cannot handle more than one UE, but found %d\n",
__func__,
UE_info->num_UEs);
if (UE_info->num_UEs == 0)
AssertFatal(nr_mac->UE_info.list[1] == NULL,
"cannot handle more than one UE\n");
if (UE == NULL)
return false;
const int UE_id = 0;
const int CC_id = 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int tda = sched_ctrl->active_ubwp ? RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 1;
if (tda < 0)
return false;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
AssertFatal(tda < tdaList->list.count,
const int temp_tda = get_ul_tda(nr_mac, scc, slot);
if (temp_tda < 0)
return false;
AssertFatal(temp_tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
tda,
temp_tda,
tdaList->list.count);
int K2 = get_K2(scc,NULL,sched_ctrl->active_ubwp, tda, mu);
int K2 = get_K2(scc,NULL,sched_ctrl->active_ubwp, temp_tda, mu);
const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]);
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu];
const int tda = get_ul_tda(nr_mac, scc, sched_slot);
if (tda < 0)
return false;
AssertFatal(tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
tda,
tdaList->list.count);
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
......@@ -515,7 +439,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, UE->rnti);
int CCEIndex = find_pdcch_candidate(nr_mac,
CC_id,
......
......@@ -34,18 +34,17 @@
extern RAN_CONTEXT_t RC;
void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id, int UE_id, NR_SRS_Resource_t *srs_resource) {
void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id,NR_UE_info_t* UE, NR_SRS_Resource_t *srs_resource) {
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
NR_ServingCellConfigCommon_t *scc = nrmac->common_channels[CC_id].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &nrmac->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_BWP_t ubwp = sched_ctrl->active_ubwp ?
sched_ctrl->active_ubwp->bwp_Common->genericParameters :
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
srs_pdu->rnti = UE_info->rnti[UE_id];
srs_pdu->rnti = UE->rnti;
srs_pdu->handle = 0;
srs_pdu->bwp_size = NRRIV2BW(ubwp.locationAndBandwidth, MAX_BWP_SIZE);;
srs_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp.locationAndBandwidth, MAX_BWP_SIZE);;
......@@ -82,7 +81,7 @@ void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id, int
srs_pdu->t_offset = get_nr_srs_offset(srs_resource->resourceType.choice.periodic->periodicityAndOffset_p);
}
void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR_SRS_Resource_t *srs_resource) {
void nr_fill_nfapi_srs(int module_id, int CC_id, NR_UE_info_t* UE, sub_frame_t slot, NR_SRS_Resource_t *srs_resource) {
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][slot];
AssertFatal(future_ul_tti_req->n_pdus <
......@@ -94,7 +93,7 @@ void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR
memset(srs_pdu, 0, sizeof(nfapi_nr_srs_pdu_t));
future_ul_tti_req->n_pdus += 1;
nr_configure_srs(srs_pdu, module_id, CC_id, UE_id, srs_resource);
nr_configure_srs(srs_pdu, module_id, CC_id, UE, srs_resource);
}
/*******************************************************************
......@@ -111,21 +110,19 @@ void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR
void nr_schedule_srs(int module_id, frame_t frame) {
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
NR_UE_info_t *UE_info = &nrmac->UE_info;
const NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UEs_t *UE_info = &nrmac->UE_info;
UE_iterator(UE_info->list, UE) {
const int CC_id = 0;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[CC_id].ServingCellConfigCommon;
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
sched_ctrl->sched_srs.frame = -1;
sched_ctrl->sched_srs.slot = -1;
sched_ctrl->sched_srs.srs_scheduled = false;
if(!UE_info->Msg4_ACKed[UE_id] || sched_ctrl->rrc_processing_timer > 0) {
if(!UE->Msg4_ACKed || sched_ctrl->rrc_processing_timer > 0) {
continue;
}
......@@ -178,11 +175,11 @@ void nr_schedule_srs(int module_id, frame_t frame) {
// Check if UE will transmit the SRS in this frame
if ( ((frame - offset/n_slots_frame)*n_slots_frame)%period == 0) {
LOG_D(NR_MAC,"Scheduling SRS reception for %d.%d\n", frame, offset%n_slots_frame);
nr_fill_nfapi_srs(module_id, CC_id, UE_id, offset%n_slots_frame, srs_resource);
nr_fill_nfapi_srs(module_id, CC_id, UE, offset%n_slots_frame, srs_resource);
sched_ctrl->sched_srs.frame = frame;
sched_ctrl->sched_srs.slot = offset%n_slots_frame;
sched_ctrl->sched_srs.srs_scheduled = true;
}
}
}
}
\ No newline at end of file
}